mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
changes to make it compatible with 64bit gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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eea60fc59c
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@ -27,6 +27,7 @@
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#include "Support/CommandLine.h"
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#include "Support/CommandLine.h"
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#include <iostream>
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#include <iostream>
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using std::cerr;
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using std::cerr;
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using std::vector;
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//******************** Internal Data Declarations ************************/
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//******************** Internal Data Declarations ************************/
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@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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void
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void
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InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec)
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InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
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{
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{
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Instruction *TermInst = (Instruction*)BB->getTerminator();
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Instruction *TermInst = (Instruction*)BB->getTerminator();
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MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
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MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
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@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
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//
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//
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if (treeRoot->opLabel != VRegListOp)
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if (treeRoot->opLabel != VRegListOp)
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{
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{
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vector<MachineInstr*> minstrVec;
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std::vector<MachineInstr*> minstrVec;
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
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assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
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@ -28,6 +28,7 @@
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#include <iostream>
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#include <iostream>
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#include <math.h>
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#include <math.h>
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using std::cerr;
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using std::cerr;
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using std::vector;
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RegAllocDebugLevel_t DEBUG_RA;
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RegAllocDebugLevel_t DEBUG_RA;
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static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",
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static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",
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@ -11,8 +11,9 @@
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#include <cstdlib>
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#include <cstdlib>
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#include <cstdio>
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#include <cstdio>
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#include <signal.h>
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#include <signal.h>
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using std::string;
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static vector<string> FilesToRemove;
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static std::vector<string> FilesToRemove;
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// IntSigs - Signals that may interrupt the program at any time.
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// IntSigs - Signals that may interrupt the program at any time.
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static const int IntSigs[] = {
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static const int IntSigs[] = {
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@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
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FilesToRemove.pop_back();
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FilesToRemove.pop_back();
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}
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}
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if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
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if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
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exit(1); // If this is an interrupt signal, exit the program
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exit(1); // If this is an interrupt signal, exit the program
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// Otherwise if it is a fault (like SEGV) reissue the signal to die...
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// Otherwise if it is a fault (like SEGV) reissue the signal to die...
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@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
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void RemoveFileOnSignal(const string &Filename) {
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void RemoveFileOnSignal(const string &Filename) {
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FilesToRemove.push_back(Filename);
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FilesToRemove.push_back(Filename);
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for_each(IntSigs, IntSigsEnd, RegisterHandler);
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std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
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for_each(KillSigs, KillSigsEnd, RegisterHandler);
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std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
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}
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}
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@ -27,6 +27,7 @@
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#include "Support/CommandLine.h"
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#include "Support/CommandLine.h"
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#include <iostream>
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#include <iostream>
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using std::cerr;
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using std::cerr;
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using std::vector;
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//******************** Internal Data Declarations ************************/
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//******************** Internal Data Declarations ************************/
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@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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void
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void
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InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec)
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InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
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{
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{
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Instruction *TermInst = (Instruction*)BB->getTerminator();
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Instruction *TermInst = (Instruction*)BB->getTerminator();
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MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
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MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
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@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
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//
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//
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if (treeRoot->opLabel != VRegListOp)
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if (treeRoot->opLabel != VRegListOp)
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{
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{
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vector<MachineInstr*> minstrVec;
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std::vector<MachineInstr*> minstrVec;
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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InstructionNode* instrNode = (InstructionNode*)treeRoot;
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assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
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assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
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@ -28,6 +28,7 @@
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#include <iostream>
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#include <iostream>
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#include <math.h>
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#include <math.h>
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using std::cerr;
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using std::cerr;
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using std::vector;
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RegAllocDebugLevel_t DEBUG_RA;
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RegAllocDebugLevel_t DEBUG_RA;
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static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",
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static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",
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@ -22,7 +22,7 @@
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#include "llvm/Instruction.h"
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#include "llvm/Instruction.h"
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#include "llvm/Constants.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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using std::vector;
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//************************ Internal Functions ******************************/
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//************************ Internal Functions ******************************/
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@ -455,16 +455,16 @@ public:
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// for an architecture.
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// for an architecture.
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//
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//
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void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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int RegType, vector<MachineInstr*>& mvec) const;
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int RegType, std::vector<MachineInstr*>& mvec) const;
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void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
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void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType, vector<MachineInstr*>& mvec) const;
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int Offset, int RegType, std::vector<MachineInstr*>& mvec) const;
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void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
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void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
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int RegType, vector<MachineInstr*>& mvec) const;
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int RegType, std::vector<MachineInstr*>& mvec) const;
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void cpValue2Value(Value *Src, Value *Dest,
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void cpValue2Value(Value *Src, Value *Dest,
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vector<MachineInstr*>& mvec) const;
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std::vector<MachineInstr*>& mvec) const;
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// To see whether a register is a volatile (i.e., whehter it must be
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// To see whether a register is a volatile (i.e., whehter it must be
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// preserved acorss calls)
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// preserved acorss calls)
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@ -52,7 +52,7 @@ namespace {
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void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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{
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{
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vector<MachineInstr*> mvec;
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std::vector<MachineInstr*> mvec;
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MachineInstr* M;
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MachineInstr* M;
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const MachineFrameInfo& frameInfo = Target.getFrameInfo();
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const MachineFrameInfo& frameInfo = Target.getFrameInfo();
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@ -4,6 +4,7 @@
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#include "llvm/Type.h"
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#include "llvm/Type.h"
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#include <iostream>
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#include <iostream>
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using std::cerr;
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using std::cerr;
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using std::vector;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Int Register Class - method for coloring a node in the interference graph.
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// Int Register Class - method for coloring a node in the interference graph.
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@ -22,6 +22,7 @@
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#include <iostream>
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#include <iostream>
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#include <values.h>
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#include <values.h>
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using std::cerr;
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using std::cerr;
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using std::vector;
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
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: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
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@ -18,6 +18,7 @@
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#include "Support/STLExtras.h"
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#include "Support/STLExtras.h"
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#include "Support/StatisticReporter.h"
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#include "Support/StatisticReporter.h"
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#include <algorithm>
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#include <algorithm>
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using std::cerr;
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static Statistic<> NumLoadStorePeepholes("raise\t\t- Number of load/store peepholes");
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static Statistic<> NumLoadStorePeepholes("raise\t\t- Number of load/store peepholes");
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static Statistic<> NumGEPInstFormed("raise\t\t- Number of other getelementptr's formed");
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static Statistic<> NumGEPInstFormed("raise\t\t- Number of other getelementptr's formed");
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@ -11,8 +11,9 @@
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#include <cstdlib>
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#include <cstdlib>
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#include <cstdio>
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#include <cstdio>
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#include <signal.h>
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#include <signal.h>
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using std::string;
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static vector<string> FilesToRemove;
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static std::vector<string> FilesToRemove;
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// IntSigs - Signals that may interrupt the program at any time.
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// IntSigs - Signals that may interrupt the program at any time.
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static const int IntSigs[] = {
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static const int IntSigs[] = {
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@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
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FilesToRemove.pop_back();
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FilesToRemove.pop_back();
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}
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}
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if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
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if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
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exit(1); // If this is an interrupt signal, exit the program
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exit(1); // If this is an interrupt signal, exit the program
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// Otherwise if it is a fault (like SEGV) reissue the signal to die...
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// Otherwise if it is a fault (like SEGV) reissue the signal to die...
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@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
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void RemoveFileOnSignal(const string &Filename) {
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void RemoveFileOnSignal(const string &Filename) {
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FilesToRemove.push_back(Filename);
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FilesToRemove.push_back(Filename);
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for_each(IntSigs, IntSigsEnd, RegisterHandler);
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std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
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for_each(KillSigs, KillSigsEnd, RegisterHandler);
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std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
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}
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}
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