changes to make it compatible with 64bit gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anand Shukla 2002-06-25 20:55:50 +00:00
parent eea60fc59c
commit cfb22d3c14
12 changed files with 27 additions and 18 deletions

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@ -27,6 +27,7 @@
#include "Support/CommandLine.h" #include "Support/CommandLine.h"
#include <iostream> #include <iostream>
using std::cerr; using std::cerr;
using std::vector;
//******************** Internal Data Declarations ************************/ //******************** Internal Data Declarations ************************/
@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
void void
InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec) InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
{ {
Instruction *TermInst = (Instruction*)BB->getTerminator(); Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst); MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
// //
if (treeRoot->opLabel != VRegListOp) if (treeRoot->opLabel != VRegListOp)
{ {
vector<MachineInstr*> minstrVec; std::vector<MachineInstr*> minstrVec;
InstructionNode* instrNode = (InstructionNode*)treeRoot; InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode); assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);

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@ -28,6 +28,7 @@
#include <iostream> #include <iostream>
#include <math.h> #include <math.h>
using std::cerr; using std::cerr;
using std::vector;
RegAllocDebugLevel_t DEBUG_RA; RegAllocDebugLevel_t DEBUG_RA;
static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc", static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",

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@ -11,8 +11,9 @@
#include <cstdlib> #include <cstdlib>
#include <cstdio> #include <cstdio>
#include <signal.h> #include <signal.h>
using std::string;
static vector<string> FilesToRemove; static std::vector<string> FilesToRemove;
// IntSigs - Signals that may interrupt the program at any time. // IntSigs - Signals that may interrupt the program at any time.
static const int IntSigs[] = { static const int IntSigs[] = {
@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
FilesToRemove.pop_back(); FilesToRemove.pop_back();
} }
if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd) if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
exit(1); // If this is an interrupt signal, exit the program exit(1); // If this is an interrupt signal, exit the program
// Otherwise if it is a fault (like SEGV) reissue the signal to die... // Otherwise if it is a fault (like SEGV) reissue the signal to die...
@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
void RemoveFileOnSignal(const string &Filename) { void RemoveFileOnSignal(const string &Filename) {
FilesToRemove.push_back(Filename); FilesToRemove.push_back(Filename);
for_each(IntSigs, IntSigsEnd, RegisterHandler); std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
for_each(KillSigs, KillSigsEnd, RegisterHandler); std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
} }

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@ -27,6 +27,7 @@
#include "Support/CommandLine.h" #include "Support/CommandLine.h"
#include <iostream> #include <iostream>
using std::cerr; using std::cerr;
using std::vector;
//******************** Internal Data Declarations ************************/ //******************** Internal Data Declarations ************************/
@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
void void
InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec) InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
{ {
Instruction *TermInst = (Instruction*)BB->getTerminator(); Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst); MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
// //
if (treeRoot->opLabel != VRegListOp) if (treeRoot->opLabel != VRegListOp)
{ {
vector<MachineInstr*> minstrVec; std::vector<MachineInstr*> minstrVec;
InstructionNode* instrNode = (InstructionNode*)treeRoot; InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode); assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);

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@ -28,6 +28,7 @@
#include <iostream> #include <iostream>
#include <math.h> #include <math.h>
using std::cerr; using std::cerr;
using std::vector;
RegAllocDebugLevel_t DEBUG_RA; RegAllocDebugLevel_t DEBUG_RA;
static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc", static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",

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@ -22,7 +22,7 @@
#include "llvm/Instruction.h" #include "llvm/Instruction.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
using std::vector;
//************************ Internal Functions ******************************/ //************************ Internal Functions ******************************/

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@ -455,16 +455,16 @@ public:
// for an architecture. // for an architecture.
// //
void cpReg2RegMI(unsigned SrcReg, unsigned DestReg, void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
int RegType, vector<MachineInstr*>& mvec) const; int RegType, std::vector<MachineInstr*>& mvec) const;
void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg, void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
int Offset, int RegType, vector<MachineInstr*>& mvec) const; int Offset, int RegType, std::vector<MachineInstr*>& mvec) const;
void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg, void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
int RegType, vector<MachineInstr*>& mvec) const; int RegType, std::vector<MachineInstr*>& mvec) const;
void cpValue2Value(Value *Src, Value *Dest, void cpValue2Value(Value *Src, Value *Dest,
vector<MachineInstr*>& mvec) const; std::vector<MachineInstr*>& mvec) const;
// To see whether a register is a volatile (i.e., whehter it must be // To see whether a register is a volatile (i.e., whehter it must be
// preserved acorss calls) // preserved acorss calls)

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@ -52,7 +52,7 @@ namespace {
void InsertPrologEpilogCode::InsertPrologCode(Function &F) void InsertPrologEpilogCode::InsertPrologCode(Function &F)
{ {
vector<MachineInstr*> mvec; std::vector<MachineInstr*> mvec;
MachineInstr* M; MachineInstr* M;
const MachineFrameInfo& frameInfo = Target.getFrameInfo(); const MachineFrameInfo& frameInfo = Target.getFrameInfo();

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@ -4,6 +4,7 @@
#include "llvm/Type.h" #include "llvm/Type.h"
#include <iostream> #include <iostream>
using std::cerr; using std::cerr;
using std::vector;
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Int Register Class - method for coloring a node in the interference graph. // Int Register Class - method for coloring a node in the interference graph.

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@ -22,6 +22,7 @@
#include <iostream> #include <iostream>
#include <values.h> #include <values.h>
using std::cerr; using std::cerr;
using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6), : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),

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@ -18,6 +18,7 @@
#include "Support/STLExtras.h" #include "Support/STLExtras.h"
#include "Support/StatisticReporter.h" #include "Support/StatisticReporter.h"
#include <algorithm> #include <algorithm>
using std::cerr;
static Statistic<> NumLoadStorePeepholes("raise\t\t- Number of load/store peepholes"); static Statistic<> NumLoadStorePeepholes("raise\t\t- Number of load/store peepholes");
static Statistic<> NumGEPInstFormed("raise\t\t- Number of other getelementptr's formed"); static Statistic<> NumGEPInstFormed("raise\t\t- Number of other getelementptr's formed");

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@ -11,8 +11,9 @@
#include <cstdlib> #include <cstdlib>
#include <cstdio> #include <cstdio>
#include <signal.h> #include <signal.h>
using std::string;
static vector<string> FilesToRemove; static std::vector<string> FilesToRemove;
// IntSigs - Signals that may interrupt the program at any time. // IntSigs - Signals that may interrupt the program at any time.
static const int IntSigs[] = { static const int IntSigs[] = {
@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
FilesToRemove.pop_back(); FilesToRemove.pop_back();
} }
if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd) if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
exit(1); // If this is an interrupt signal, exit the program exit(1); // If this is an interrupt signal, exit the program
// Otherwise if it is a fault (like SEGV) reissue the signal to die... // Otherwise if it is a fault (like SEGV) reissue the signal to die...
@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
void RemoveFileOnSignal(const string &Filename) { void RemoveFileOnSignal(const string &Filename) {
FilesToRemove.push_back(Filename); FilesToRemove.push_back(Filename);
for_each(IntSigs, IntSigsEnd, RegisterHandler); std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
for_each(KillSigs, KillSigsEnd, RegisterHandler); std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
} }