6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

changes to make it compatible with 64bit gcc

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anand Shukla 2002-06-25 20:55:50 +00:00
parent eea60fc59c
commit cfb22d3c14
12 changed files with 27 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/InstrSelection/InstrSelection.cpp
View File

@ -27,6 +27,7 @@
#include "Support/CommandLine.h"
#include <iostream>
using std::cerr;
using std::vector;
//******************** Internal Data Declarations ************************/
@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
//-------------------------------------------------------------------------
void
InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec)
InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
{
Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
//
if (treeRoot->opLabel != VRegListOp)
{
vector<MachineInstr*> minstrVec;
std::vector<MachineInstr*> minstrVec;
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);

1
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -28,6 +28,7 @@
#include <iostream>
#include <math.h>
using std::cerr;
using std::vector;
RegAllocDebugLevel_t DEBUG_RA;
static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",

9
lib/Support/Signals.cpp
View File

@ -11,8 +11,9 @@
#include <cstdlib>
#include <cstdio>
#include <signal.h>
using std::string;
static vector<string> FilesToRemove;
static std::vector<string> FilesToRemove;
// IntSigs - Signals that may interrupt the program at any time.
static const int IntSigs[] = {
@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
FilesToRemove.pop_back();
}
if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
exit(1); // If this is an interrupt signal, exit the program
// Otherwise if it is a fault (like SEGV) reissue the signal to die...
@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
void RemoveFileOnSignal(const string &Filename) {
FilesToRemove.push_back(Filename);
for_each(IntSigs, IntSigsEnd, RegisterHandler);
for_each(KillSigs, KillSigsEnd, RegisterHandler);
std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
}

5
lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
View File

@ -27,6 +27,7 @@
#include "Support/CommandLine.h"
#include <iostream>
using std::cerr;
using std::vector;
//******************** Internal Data Declarations ************************/
@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
//-------------------------------------------------------------------------
void
InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec)
InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
{
Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
//
if (treeRoot->opLabel != VRegListOp)
{
vector<MachineInstr*> minstrVec;
std::vector<MachineInstr*> minstrVec;
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);

1
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -28,6 +28,7 @@
#include <iostream>
#include <math.h>
using std::cerr;
using std::vector;
RegAllocDebugLevel_t DEBUG_RA;
static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",

2
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -22,7 +22,7 @@
#include "llvm/Instruction.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
using std::vector;
//************************ Internal Functions ******************************/

8
lib/Target/SparcV9/SparcV9Internals.h
View File

@ -455,16 +455,16 @@ public:
// for an architecture.
//
void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
int RegType, vector<MachineInstr*>& mvec) const;
int RegType, std::vector<MachineInstr*>& mvec) const;
void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
int Offset, int RegType, vector<MachineInstr*>& mvec) const;
int Offset, int RegType, std::vector<MachineInstr*>& mvec) const;
void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
int RegType, vector<MachineInstr*>& mvec) const;
int RegType, std::vector<MachineInstr*>& mvec) const;
void cpValue2Value(Value *Src, Value *Dest,
vector<MachineInstr*>& mvec) const;
std::vector<MachineInstr*>& mvec) const;
// To see whether a register is a volatile (i.e., whehter it must be
// preserved acorss calls)

2
lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
View File

@ -52,7 +52,7 @@ namespace {
void InsertPrologEpilogCode::InsertPrologCode(Function &F)
{
vector<MachineInstr*> mvec;
std::vector<MachineInstr*> mvec;
MachineInstr* M;
const MachineFrameInfo& frameInfo = Target.getFrameInfo();

1
lib/Target/SparcV9/SparcV9RegClassInfo.cpp
View File

@ -4,6 +4,7 @@
#include "llvm/Type.h"
#include <iostream>
using std::cerr;
using std::vector;
//-----------------------------------------------------------------------------
// Int Register Class - method for coloring a node in the interference graph.

1
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -22,6 +22,7 @@
#include <iostream>
#include <values.h>
using std::cerr;
using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
: MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),

1
lib/Transforms/LevelRaise.cpp
View File

@ -18,6 +18,7 @@
#include "Support/STLExtras.h"
#include "Support/StatisticReporter.h"
#include <algorithm>
using std::cerr;
static Statistic<> NumLoadStorePeepholes("raise\t\t- Number of load/store peepholes");
static Statistic<> NumGEPInstFormed("raise\t\t- Number of other getelementptr's formed");

9
support/lib/Support/Signals.cpp
View File

@ -11,8 +11,9 @@
#include <cstdlib>
#include <cstdio>
#include <signal.h>
using std::string;
static vector<string> FilesToRemove;
static std::vector<string> FilesToRemove;
// IntSigs - Signals that may interrupt the program at any time.
static const int IntSigs[] = {
@ -36,7 +37,7 @@ static void SignalHandler(int Sig) {
FilesToRemove.pop_back();
}
if (find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
if (std::find(IntSigs, IntSigsEnd, Sig) != IntSigsEnd)
exit(1); // If this is an interrupt signal, exit the program
// Otherwise if it is a fault (like SEGV) reissue the signal to die...
@ -48,6 +49,6 @@ static void RegisterHandler(int Signal) { signal(Signal, SignalHandler); }
void RemoveFileOnSignal(const string &Filename) {
FilesToRemove.push_back(Filename);
for_each(IntSigs, IntSigsEnd, RegisterHandler);
for_each(KillSigs, KillSigsEnd, RegisterHandler);
std::for_each(IntSigs, IntSigsEnd, RegisterHandler);
std::for_each(KillSigs, KillSigsEnd, RegisterHandler);
}