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Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
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3eff4af42d
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cfd0e1f3ae
@ -3930,24 +3930,24 @@ def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
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// VTBL : Vector Table Lookup
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def VTBL1
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: N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
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"vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
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: N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
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(ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
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"vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
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[(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VTBL2
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: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
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"vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
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: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
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(ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
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"vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
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def VTBL3
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: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
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"vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
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: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
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(ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
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"vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
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def VTBL4
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: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
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: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
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(ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
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NVTBLFrm, IIC_VTB4,
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"vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
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"vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
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} // hasExtraSrcRegAllocReq = 1
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def VTBL2Pseudo
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@ -3959,27 +3959,27 @@ def VTBL4Pseudo
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// VTBX : Vector Table Extension
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def VTBX1
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: N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
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"vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
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DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
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: N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
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(ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
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"vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
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[(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
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DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VTBX2
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: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
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"vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
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: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
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(ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
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"vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
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def VTBX3
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: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
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: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
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(ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
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NVTBLFrm, IIC_VTBX3,
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"vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
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"$orig = $dst", []>;
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"vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
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"$orig = $Vd", []>;
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def VTBX4
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: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
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DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
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"vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
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"$orig = $dst", []>;
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: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
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DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
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"vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
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"$orig = $Vd", []>;
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} // hasExtraSrcRegAllocReq = 1
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def VTBX2Pseudo
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102
test/MC/ARM/neon-table-encoding.ll
Normal file
102
test/MC/ARM/neon-table-encoding.ll
Normal file
@ -0,0 +1,102 @@
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; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
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%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x2_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
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; CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
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%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
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ret <8 x i8> %tmp5
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}
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define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x3_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
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; CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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; CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = load <8 x i8>* %C
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; CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3]
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%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x2_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
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%tmp5 = load <8 x i8>* %C
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; CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3]
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x3_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
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%tmp6 = load <8 x i8>* %C
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; CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3]
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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%tmp7 = load <8 x i8>* %C
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; CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3]
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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ret <8 x i8> %tmp8
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}
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declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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