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R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -351,7 +351,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
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} else if (N->getValueType(0) == MVT::i64) {
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RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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} else {
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@ -87,8 +87,9 @@ define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)
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}
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; FUNC-LABEL: @zextload_global_i8_to_i64
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; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0
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; SI: BUFFER_LOAD_UBYTE [[LOAD:v[0-9]+]],
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]]
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; SI: BUFFER_STORE_DWORDX2
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define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
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%a = load i8 addrspace(1)* %in, align 8
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@ -98,8 +99,9 @@ define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)*
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}
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; FUNC-LABEL: @zextload_global_i16_to_i64
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; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0
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; SI: BUFFER_LOAD_USHORT [[LOAD:v[0-9]+]],
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]]
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; SI: BUFFER_STORE_DWORDX2
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define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
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%a = load i16 addrspace(1)* %in, align 8
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@ -109,8 +111,9 @@ define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)
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}
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; FUNC-LABEL: @zextload_global_i32_to_i64
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; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0
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; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]],
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0
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; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]]
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; SI: BUFFER_STORE_DWORDX2
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define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%a = load i32 addrspace(1)* %in, align 8
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@ -6,8 +6,9 @@
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; SI-CHECK: @test
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; SI-CHECK: V_MOV_B32_e32 v[[ZERO:[0-9]]], 0
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; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[ZERO]]{{\]}}
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; SI-CHECK: S_MOV_B32 [[ZERO:s[0-9]]], 0
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; SI-CHECK: V_MOV_B32_e32 v[[V_ZERO:[0-9]]], [[ZERO]]
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; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[V_ZERO]]{{\]}}
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define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = mul i32 %a, %b
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@ -30,7 +31,7 @@ entry:
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; SI-CHECK-LABEL: @zext_i1_to_i64
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; SI-CHECK: V_CMP_EQ_I32
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; SI-CHECK: V_CNDMASK_B32
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; SI-CHECK: V_MOV_B32_e32 v{{[0-9]+}}, 0
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; SI-CHECK: S_MOV_B32 s{{[0-9]+}}, 0
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define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%ext = zext i1 %cmp to i64
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