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Allow lowering for palignr instructions for mmx sized vectors. Add
patterns to handle the lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101331 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7949,9 +7949,9 @@ bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
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bool
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X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
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EVT VT) const {
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// Only do shuffles on 128-bit vector types for now.
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// Very little shuffling can be done for 64-bit vectors right now.
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if (VT.getSizeInBits() == 64)
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return false;
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return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
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// FIXME: pshufb, blends, shifts.
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return (VT.getVectorNumElements() == 2 ||
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@ -2915,6 +2915,7 @@ defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128>;
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// palignr patterns.
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let Constraints = "$src1 = $dst" in {
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def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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@ -2935,7 +2936,6 @@ let Constraints = "$src1 = $dst" in {
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[]>, OpSize;
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}
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// palignr patterns.
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def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
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(PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
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Requires<[HasSSSE3]>;
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@ -2944,6 +2944,26 @@ def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
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(i8 imm:$src3)),
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(PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
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(PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
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(PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
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(PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
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(PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
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(PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
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(PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
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