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Add an ARM RSBrr instruction for disassembly only.

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Partial fix for PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-05 18:23:43 +00:00
parent a330d4c3ea
commit cff7178844
2 changed files with 13 additions and 1 deletions
lib/Target/ARM
ARMInstrInfo.td
test/MC/Disassembler
arm-tests.txt

10
lib/Target/ARM/ARMInstrInfo.td

@ -1629,13 +1629,21 @@ defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
// These don't define reg/reg forms, because they are handled above.
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", "\t$dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
let Inst{25} = 1;
}
// The reg/reg form is only defined for the disassembler; for codegen it is
// equivalent to SUBrr.
def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
IIC_iALUr, "rsb", "\t$dst, $a, $b",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{11-4} = 0b00000000;
}
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "\t$dst, $a, $b",
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {

4
test/MC/Disassembler/arm-tests.txt

@ -61,6 +61,10 @@
# CHECK: rfedb r0!
0x00 0x0a 0x30 0xf9
# CHECK-NOT: rsbeq r0, r2, r0, lsl #0
# CHECK: rsbeq r0, r2, r0
0x00 0x00 0x62 0x00
# CHECK: sbcs r0, pc, #1
0x01 0x00 0xdf 0xe2