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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
AVX-512: select operation for i1 vectors
like: select i1 %cond, <16 x i1> %a, <16 x i1> %b. I added pseudo-CMOV patterns to resolve the "select". Added tests for KNL and SKX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237106 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1365,6 +1365,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
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setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
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setOperationAction(ISD::ADD, MVT::v8i64, Legal);
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setOperationAction(ISD::ADD, MVT::v16i32, Legal);
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@ -1467,6 +1469,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
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for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
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const MVT VT = (MVT::SimpleValueType)i;
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@ -1494,6 +1498,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
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setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
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setOperationAction(ISD::AND, MVT::v8i32, Legal);
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setOperationAction(ISD::OR, MVT::v8i32, Legal);
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@ -13609,6 +13615,17 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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if (VT == MVT::v4i1 || VT == MVT::v2i1) {
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SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
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Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
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DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
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Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
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DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
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SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
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Cond, Op1, Op2);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
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}
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if (Cond.getOpcode() == ISD::SETCC) {
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SDValue NewCond = LowerSETCC(Cond, DAG);
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if (NewCond.getNode())
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@ -19481,6 +19498,10 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::CMOV_RFP32:
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case X86::CMOV_RFP64:
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case X86::CMOV_RFP80:
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case X86::CMOV_V8I1:
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case X86::CMOV_V16I1:
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case X86::CMOV_V32I1:
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case X86::CMOV_V64I1:
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return EmitLoweredSelect(MI, BB);
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case X86::FP32_TO_INT16_IN_MEM:
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@ -518,6 +518,10 @@ let usesCustomInserter = 1, Uses = [EFLAGS] in {
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defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
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defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
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defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
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defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
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defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
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defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
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defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
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} // usesCustomInserter = 1, Uses = [EFLAGS]
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//===----------------------------------------------------------------------===//
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@ -207,3 +207,78 @@ true:
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false:
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ret void
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}
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; KNL-LABEL: test8
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; KNL: vpxord %zmm2, %zmm2, %zmm2
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; KNL: jg
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; KNL: vpcmpltud %zmm2, %zmm1, %k1
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; KNL: jmp
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; KNL: vpcmpgtd %zmm2, %zmm0, %k1
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; SKX-LABEL: test8
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; SKX: jg
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; SKX: vpcmpltud {{.*}}, %k0
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; SKX: vpmovm2b
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; SKX: vpcmpgtd {{.*}}, %k0
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; SKX: vpmovm2b
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define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) {
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%cond = icmp sgt i32 %a1, %b1
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%cmp1 = icmp sgt <16 x i32> %a, zeroinitializer
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%cmp2 = icmp ult <16 x i32> %b, zeroinitializer
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%mix = select i1 %cond, <16 x i1> %cmp1, <16 x i1> %cmp2
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%res = sext <16 x i1> %mix to <16 x i8>
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ret <16 x i8> %res
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}
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; KNL-LABEL: test9
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; KNL: jg
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; KNL: vpmovsxbd %xmm1, %zmm0
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; KNL: jmp
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; KNL: vpmovsxbd %xmm0, %zmm0
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; SKX-LABEL: test9
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; SKX: vpmovb2m %xmm1, %k0
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; SKX: vpmovm2b %k0, %xmm0
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; SKX: retq
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; SKX: vpmovb2m %xmm0, %k0
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; SKX: vpmovm2b %k0, %xmm0
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define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) {
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%mask = icmp sgt i32 %a1, %b1
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%c = select i1 %mask, <16 x i1>%a, <16 x i1>%b
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ret <16 x i1>%c
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}
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; KNL-LABEL: test10
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; KNL: jg
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; KNL: vpmovsxwq %xmm1, %zmm0
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; KNL: jmp
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; KNL: vpmovsxwq %xmm0, %zmm0
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; SKX-LABEL: test10
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; SKX: jg
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; SKX: vpmovw2m %xmm1, %k0
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; SKX: vpmovm2w %k0, %xmm0
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; SKX: retq
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; SKX: vpmovw2m %xmm0, %k0
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; SKX: vpmovm2w %k0, %xmm0
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define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) {
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%mask = icmp sgt i32 %a1, %b1
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%c = select i1 %mask, <8 x i1>%a, <8 x i1>%b
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ret <8 x i1>%c
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}
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; SKX-LABEL: test11
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; SKX: jg
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; SKX: vpmovd2m %xmm1, %k0
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; SKX: vpmovm2d %k0, %xmm0
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; SKX: retq
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; SKX: vpmovd2m %xmm0, %k0
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; SKX: vpmovm2d %k0, %xmm0
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define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) {
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%mask = icmp sgt i32 %a1, %b1
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%c = select i1 %mask, <4 x i1>%a, <4 x i1>%b
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ret <4 x i1>%c
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}
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