mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
Now add ordering to SDNodes created by the massive intrinsic lowering function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91863 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
856ff41079
commit
d0283fa69f
@ -4196,6 +4196,8 @@ SelectionDAGBuilder::visitPow(CallInst &I) {
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const char *
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SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DebugLoc dl = getCurDebugLoc();
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SDValue Res;
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switch (Intrinsic) {
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default:
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// By default, turn this into a target intrinsic node.
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@ -4205,26 +4207,33 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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case Intrinsic::vaend: visitVAEnd(I); return 0;
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case Intrinsic::vacopy: visitVACopy(I); return 0;
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case Intrinsic::returnaddress:
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setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::frameaddress:
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setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::setjmp:
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return "_setjmp"+!TLI.usesUnderscoreSetJmp();
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break;
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case Intrinsic::longjmp:
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return "_longjmp"+!TLI.usesUnderscoreLongJmp();
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break;
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case Intrinsic::memcpy: {
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SDValue Op1 = getValue(I.getOperand(1));
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SDValue Op2 = getValue(I.getOperand(2));
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SDValue Op3 = getValue(I.getOperand(3));
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unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
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DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
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I.getOperand(1), 0, I.getOperand(2), 0));
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Res = DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
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I.getOperand(1), 0, I.getOperand(2), 0);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::memset: {
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@ -4232,8 +4241,11 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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SDValue Op2 = getValue(I.getOperand(2));
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SDValue Op3 = getValue(I.getOperand(3));
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unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
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DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
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I.getOperand(1), 0));
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Res = DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
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I.getOperand(1), 0);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::memmove: {
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@ -4249,13 +4261,19 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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Size = C->getZExtValue();
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if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
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AliasAnalysis::NoAlias) {
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DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
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I.getOperand(1), 0, I.getOperand(2), 0));
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Res = DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
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I.getOperand(1), 0, I.getOperand(2), 0);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
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I.getOperand(1), 0, I.getOperand(2), 0));
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Res = DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
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I.getOperand(1), 0, I.getOperand(2), 0);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::dbg_stoppoint:
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@ -4308,6 +4326,8 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
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setValue(&I, Op);
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DAG.setRoot(Op.getValue(1));
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if (DisableScheduling)
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DAG.AssignOrdering(Op.getNode(), SDNodeOrder);
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return 0;
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}
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@ -4334,7 +4354,12 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DAG.setRoot(Op.getValue(1));
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setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
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Res = DAG.getSExtOrTrunc(Op, dl, MVT::i32);
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setValue(&I, Res);
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if (DisableScheduling) {
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DAG.AssignOrdering(Op.getNode(), SDNodeOrder);
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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return 0;
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}
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@ -4344,14 +4369,16 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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if (MMI) {
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// Find the type id for the given typeinfo.
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GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
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unsigned TypeID = MMI->getTypeIDFor(GV);
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setValue(&I, DAG.getConstant(TypeID, MVT::i32));
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Res = DAG.getConstant(TypeID, MVT::i32);
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} else {
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// Return something different to eh_selector.
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setValue(&I, DAG.getConstant(1, MVT::i32));
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Res = DAG.getConstant(1, MVT::i32);
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}
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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@ -4359,11 +4386,14 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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case Intrinsic::eh_return_i64:
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if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
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MMI->setCallsEHReturn(true);
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DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
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MVT::Other,
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getControlRoot(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2))));
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Res = DAG.getNode(ISD::EH_RETURN, dl,
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MVT::Other,
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getControlRoot(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2)));
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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} else {
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setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
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}
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@ -4373,26 +4403,28 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
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MMI->setCallsUnwindInit(true);
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}
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return 0;
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case Intrinsic::eh_dwarf_cfa: {
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EVT VT = getValue(I.getOperand(1)).getValueType();
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SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
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TLI.getPointerTy());
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SDValue Offset = DAG.getNode(ISD::ADD, dl,
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TLI.getPointerTy(),
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DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
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TLI.getPointerTy()),
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CfaArg);
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setValue(&I, DAG.getNode(ISD::ADD, dl,
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SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
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TLI.getPointerTy(),
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DAG.getNode(ISD::FRAMEADDR, dl,
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TLI.getPointerTy(),
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DAG.getConstant(0,
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TLI.getPointerTy())),
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Offset));
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DAG.getConstant(0, TLI.getPointerTy()));
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Res = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
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FA, Offset);
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setValue(&I, Res);
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if (DisableScheduling) {
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DAG.AssignOrdering(CfaArg.getNode(), SDNodeOrder);
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DAG.AssignOrdering(Offset.getNode(), SDNodeOrder);
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DAG.AssignOrdering(FA.getNode(), SDNodeOrder);
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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}
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return 0;
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}
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case Intrinsic::convertff:
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@ -4417,36 +4449,50 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
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}
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EVT DestVT = TLI.getValueType(I.getType());
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Value* Op1 = I.getOperand(1);
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setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
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DAG.getValueType(DestVT),
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DAG.getValueType(getValue(Op1).getValueType()),
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getValue(I.getOperand(2)),
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getValue(I.getOperand(3)),
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Code));
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Value *Op1 = I.getOperand(1);
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Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
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DAG.getValueType(DestVT),
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DAG.getValueType(getValue(Op1).getValueType()),
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getValue(I.getOperand(2)),
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getValue(I.getOperand(3)),
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Code);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::sqrt:
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setValue(&I, DAG.getNode(ISD::FSQRT, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::FSQRT, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::powi:
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setValue(&I, DAG.getNode(ISD::FPOWI, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2))));
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Res = DAG.getNode(ISD::FPOWI, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)),
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getValue(I.getOperand(2)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::sin:
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setValue(&I, DAG.getNode(ISD::FSIN, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::FSIN, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::cos:
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setValue(&I, DAG.getNode(ISD::FCOS, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::FCOS, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::log:
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visitLog(I);
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@ -4468,55 +4514,74 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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return 0;
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case Intrinsic::pcmarker: {
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SDValue Tmp = getValue(I.getOperand(1));
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DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
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Res = DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::readcyclecounter: {
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SDValue Op = getRoot();
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SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
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DAG.getVTList(MVT::i64, MVT::Other),
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&Op, 1);
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setValue(&I, Tmp);
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DAG.setRoot(Tmp.getValue(1));
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Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
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DAG.getVTList(MVT::i64, MVT::Other),
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&Op, 1);
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setValue(&I, Res);
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DAG.setRoot(Res.getValue(1));
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::bswap:
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setValue(&I, DAG.getNode(ISD::BSWAP, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1))));
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Res = DAG.getNode(ISD::BSWAP, dl,
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getValue(I.getOperand(1)).getValueType(),
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getValue(I.getOperand(1)));
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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case Intrinsic::cttz: {
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SDValue Arg = getValue(I.getOperand(1));
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EVT Ty = Arg.getValueType();
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SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
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setValue(&I, result);
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Res = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::ctlz: {
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SDValue Arg = getValue(I.getOperand(1));
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EVT Ty = Arg.getValueType();
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SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
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setValue(&I, result);
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Res = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::ctpop: {
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SDValue Arg = getValue(I.getOperand(1));
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EVT Ty = Arg.getValueType();
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SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
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setValue(&I, result);
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Res = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::stacksave: {
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SDValue Op = getRoot();
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SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
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DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
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setValue(&I, Tmp);
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DAG.setRoot(Tmp.getValue(1));
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Res = DAG.getNode(ISD::STACKSAVE, dl,
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DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
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setValue(&I, Res);
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DAG.setRoot(Res.getValue(1));
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::stackrestore: {
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SDValue Tmp = getValue(I.getOperand(1));
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DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
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Res = getValue(I.getOperand(1));
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Res = DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::stackprotector: {
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@ -4534,11 +4599,13 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
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// Store the stack protector onto the stack.
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SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
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PseudoSourceValue::getFixedStack(FI),
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0, true);
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setValue(&I, Result);
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DAG.setRoot(Result);
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Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
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PseudoSourceValue::getFixedStack(FI),
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0, true);
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setValue(&I, Res);
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DAG.setRoot(Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::objectsize: {
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@ -4551,9 +4618,13 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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EVT Ty = Arg.getValueType();
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if (CI->getZExtValue() < 2)
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setValue(&I, DAG.getConstant(-1ULL, Ty));
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Res = DAG.getConstant(-1ULL, Ty);
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else
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setValue(&I, DAG.getConstant(0, Ty));
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Res = DAG.getConstant(0, Ty);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return 0;
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}
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case Intrinsic::var_annotation:
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@ -4571,15 +4642,16 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
Ops[4] = DAG.getSrcValue(I.getOperand(1));
|
||||
Ops[5] = DAG.getSrcValue(F);
|
||||
|
||||
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
|
||||
DAG.getVTList(TLI.getPointerTy(), MVT::Other),
|
||||
Ops, 6);
|
||||
Res = DAG.getNode(ISD::TRAMPOLINE, dl,
|
||||
DAG.getVTList(TLI.getPointerTy(), MVT::Other),
|
||||
Ops, 6);
|
||||
|
||||
setValue(&I, Tmp);
|
||||
DAG.setRoot(Tmp.getValue(1));
|
||||
setValue(&I, Res);
|
||||
DAG.setRoot(Res.getValue(1));
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
|
||||
case Intrinsic::gcroot:
|
||||
if (GFI) {
|
||||
Value *Alloca = I.getOperand(1);
|
||||
@ -4589,22 +4661,22 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
GFI->addStackRoot(FI->getIndex(), TypeMap);
|
||||
}
|
||||
return 0;
|
||||
|
||||
case Intrinsic::gcread:
|
||||
case Intrinsic::gcwrite:
|
||||
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
|
||||
return 0;
|
||||
|
||||
case Intrinsic::flt_rounds: {
|
||||
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
|
||||
case Intrinsic::flt_rounds:
|
||||
Res = DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32);
|
||||
setValue(&I, Res);
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
|
||||
case Intrinsic::trap: {
|
||||
DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
|
||||
case Intrinsic::trap:
|
||||
Res = DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot());
|
||||
DAG.setRoot(Res);
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
|
||||
case Intrinsic::uadd_with_overflow:
|
||||
return implVisitAluOverflow(I, ISD::UADDO);
|
||||
case Intrinsic::sadd_with_overflow:
|
||||
@ -4624,7 +4696,10 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
Ops[1] = getValue(I.getOperand(1));
|
||||
Ops[2] = getValue(I.getOperand(2));
|
||||
Ops[3] = getValue(I.getOperand(3));
|
||||
DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
|
||||
Res = DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4);
|
||||
DAG.setRoot(Res);
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -4634,7 +4709,10 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
for (int x = 1; x < 6; ++x)
|
||||
Ops[x] = getValue(I.getOperand(x));
|
||||
|
||||
DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
|
||||
Res = DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6);
|
||||
DAG.setRoot(Res);
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
case Intrinsic::atomic_cmp_swap: {
|
||||
@ -4649,6 +4727,8 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
I.getOperand(1));
|
||||
setValue(&I, L);
|
||||
DAG.setRoot(L.getValue(1));
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(L.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
}
|
||||
case Intrinsic::atomic_load_add:
|
||||
@ -4677,7 +4757,10 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
||||
case Intrinsic::invariant_start:
|
||||
case Intrinsic::lifetime_start:
|
||||
// Discard region information.
|
||||
setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
|
||||
Res = DAG.getUNDEF(TLI.getPointerTy());
|
||||
setValue(&I, Res);
|
||||
if (DisableScheduling)
|
||||
DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
|
||||
return 0;
|
||||
case Intrinsic::invariant_end:
|
||||
case Intrinsic::lifetime_end:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user