mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Convert to the new TargetMachine interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13952 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
289809d139
commit
d029cd2d5a
@ -220,8 +220,8 @@ void InstructionSelection::InsertCodeForPhis(Function &F) {
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MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN);
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for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) {
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std::vector<MachineInstr*> mvec, CpVec;
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Target.getRegInfo().cpValue2Value(PN->getIncomingValue(i), PhiCpRes,
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mvec);
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Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
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PhiCpRes, mvec);
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for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
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MI != mvec.end(); ++MI) {
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std::vector<MachineInstr*> CpVec2 =
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@ -235,7 +235,7 @@ void InstructionSelection::InsertCodeForPhis(Function &F) {
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}
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// Insert a copy instruction from PhiCpRes to PN.
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std::vector<MachineInstr*> mvec;
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Target.getRegInfo().cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN),
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Target.getRegInfo()->cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN),
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mvec);
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BB->insert(BB->begin(), mvec.begin(), mvec.end());
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MCforPN.insert (MCforPN.end (), mvec.begin (), mvec.end ());
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@ -40,7 +40,7 @@ InsertCodeToLoadConstant(Function *F,
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MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
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TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
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target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
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target.getInstrInfo()->CreateCodeToLoadConst(target, F, opValue, tmpReg,
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loadConstVec, mcfi);
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// Record the mapping from the tmp VM instruction to machine instruction.
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@ -66,14 +66,14 @@ ChooseRegOrImmed(int64_t intValue,
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getImmedValue = 0;
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if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) {
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target.getInstrInfo()->constantFitsInImmedField(opCode, intValue)) {
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opType = isSigned? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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} else if (intValue == 0 &&
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target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
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target.getRegInfo()->getZeroRegNum() != (unsigned)-1) {
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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getMachineRegNum = target.getRegInfo()->getZeroRegNum();
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}
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return opType;
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@ -95,7 +95,7 @@ ChooseRegOrImmed(Value* val,
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// TargetInstrInfo::ConvertConstantToIntType() does the right conversions:
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bool isValidConstant;
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uint64_t valueToUse =
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target.getInstrInfo().ConvertConstantToIntType(target, val, val->getType(),
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target.getInstrInfo()->ConvertConstantToIntType(target, val, val->getType(),
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isValidConstant);
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if (! isValidConstant)
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return MachineOperand::MO_VirtualRegister;
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@ -130,7 +130,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
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std::vector<MachineInstr*> MVec;
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MachineOpCode opCode = minstr->getOpcode();
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const TargetInstrInfo& instrInfo = target.getInstrInfo();
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const TargetInstrInfo& instrInfo = *target.getInstrInfo();
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int resultPos = instrInfo.getResultPos(opCode);
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int immedPos = instrInfo.getImmedConstantPos(opCode);
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@ -295,12 +295,12 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
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// If the current machine instruction has delay slots, mark values
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// used by this instruction as live before and after each delay slot
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// instruction (After(MI) is the same as Before(MI+1) except for last MI).
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if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpcode())) {
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if (unsigned DS = TM.getInstrInfo()->getNumDelaySlots(MI->getOpcode())) {
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MachineBasicBlock::const_iterator fwdMII = MII.base(); // ptr to *next* MI
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for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
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assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
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const MachineInstr* DelaySlotMI = fwdMII;
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if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpcode())) {
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if (! TM.getInstrInfo()->isNop(DelaySlotMI->getOpcode())) {
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set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
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if (i+1 == DS)
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set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
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@ -29,7 +29,7 @@ unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
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LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
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std::vector<RegClass *> &RCL)
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: Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
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: Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { }
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LiveRangeInfo::~LiveRangeInfo() {
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@ -176,8 +176,8 @@ void LiveRangeInfo::constructLiveRanges() {
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// If the machine instruction is a call/return instruction, add it to
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// CallRetInstrList for processing its args, ret value, and ret addr.
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//
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if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
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TM.getInstrInfo().isCall(MInst->getOpcode()))
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if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
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TM.getInstrInfo()->isCall(MInst->getOpcode()))
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CallRetInstrList.push_back(MInst);
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// iterate over explicit MI operands and create a new LR
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@ -244,9 +244,9 @@ void LiveRangeInfo::suggestRegs4CallRets() {
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MachineInstr *MInst = *It;
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MachineOpCode OpCode = MInst->getOpcode();
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if ((TM.getInstrInfo()).isReturn(OpCode))
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if (TM.getInstrInfo()->isReturn(OpCode))
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MRI.suggestReg4RetValue(MInst, *this);
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else if ((TM.getInstrInfo()).isCall(OpCode))
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else if (TM.getInstrInfo()->isCall(OpCode))
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MRI.suggestRegs4CallArgs(MInst, *this);
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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@ -240,7 +240,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
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// get the LV set after the instruction
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
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bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
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bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode());
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if (isCallInst) {
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// set the isCallInterference flag of each live range which extends
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@ -265,7 +265,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
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// another. This must be done because pseudo-instructions may be
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// expanded to multiple instructions by the assembler, so all the
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// operands must get distinct registers.
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if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
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if (TM.getInstrInfo()->isPseudoInstr(MInst->getOpcode()))
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addInterf4PseudoInstr(MInst);
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// Also add interference for any implicit definitions in a machine
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@ -453,7 +453,7 @@ void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
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// Now insert caller-saving code before/after the call.
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// Do this before inserting spill code since some registers must be
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// used by save/restore and spill code should not use those registers.
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if (TM.getInstrInfo().isCall(Opcode)) {
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if (TM.getInstrInfo()->isCall(Opcode)) {
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AddedInstrns &AI = AddedInstrMap[MInst];
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insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
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MBB.getBasicBlock());
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@ -497,7 +497,7 @@ void PhyRegAlloc::updateMachineCode()
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// their assigned registers or insert spill code, as appropriate.
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// Also, fix operands of call/return instructions.
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for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
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if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
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if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode()))
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updateInstruction(MII, MBB);
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// Now, move code out of delay slots of branches and returns if needed.
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@ -516,15 +516,15 @@ void PhyRegAlloc::updateMachineCode()
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// If so, we need to handle spill differently but annulling is not yet used.
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for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
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if (unsigned delaySlots =
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TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
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TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
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MachineBasicBlock::iterator DelaySlotMI = next(MII);
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assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
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// Check the 2 conditions above:
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// (1) Does a branch need instructions added after it?
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// (2) O/w does delay slot instr. need instrns before or after?
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bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
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TM.getInstrInfo().isReturn(MII->getOpcode()));
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bool isBranch = (TM.getInstrInfo()->isBranch(MII->getOpcode()) ||
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TM.getInstrInfo()->isReturn(MII->getOpcode()));
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bool cond1 = (isBranch &&
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AddedInstrMap.count(MII) &&
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AddedInstrMap[MII].InstrnsAfter.size() > 0);
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@ -549,7 +549,7 @@ void PhyRegAlloc::updateMachineCode()
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// instruction out of the delay slot). On cond2 we need
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// to insert a nop in place of the moved instruction
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if (cond2) {
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MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
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MBB.insert(MII, BuildMI(TM.getInstrInfo()->getNOPOpCode(),1));
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}
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}
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else {
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@ -565,7 +565,7 @@ void PhyRegAlloc::updateMachineCode()
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MachineInstr *MInst = MII;
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// do not process Phis
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if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
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if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode()))
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continue;
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// if there are any added instructions...
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@ -573,11 +573,11 @@ void PhyRegAlloc::updateMachineCode()
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AddedInstrns &CallAI = AddedInstrMap[MInst];
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#ifndef NDEBUG
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bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
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TM.getInstrInfo().isReturn(MInst->getOpcode()));
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bool isBranch = (TM.getInstrInfo()->isBranch(MInst->getOpcode()) ||
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TM.getInstrInfo()->isReturn(MInst->getOpcode()));
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assert((!isBranch ||
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AddedInstrMap[MInst].InstrnsAfter.size() <=
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TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
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TM.getInstrInfo()->getNumDelaySlots(MInst->getOpcode())) &&
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"Cannot put more than #delaySlots instrns after "
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"branch or return! Need to handle temps differently.");
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#endif
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@ -628,9 +628,9 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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MachineInstr *MInst = MII;
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const BasicBlock *BB = MBB.getBasicBlock();
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assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
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assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) &&
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"Outgoing arg of a call must be handled elsewhere (func arg ok)");
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assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
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assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) &&
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"Return value of a ret must be handled elsewhere");
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MachineOperand& Op = MInst->getOperand(OpNum);
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@ -649,7 +649,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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// trample those! Verify that the set is included in the LV set before MInst.
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if (MII != MBB.begin()) {
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MachineBasicBlock::iterator PredMI = prior(MII);
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if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
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if (unsigned DS = TM.getInstrInfo()->getNumDelaySlots(PredMI->getOpcode()))
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assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
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.empty() && "Live-var set before branch should be included in "
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"live-var set of each delay slot instruction!");
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@ -735,7 +735,7 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
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std::vector<MachineInstr*> &instrnsAfter,
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MachineInstr *CallMI,
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const BasicBlock *BB) {
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assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
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assert(TM.getInstrInfo()->isCall(CallMI->getOpcode()));
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// hash set to record which registers were saved/restored
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hash_set<unsigned> PushedRegSet;
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@ -1326,8 +1326,8 @@ bool PhyRegAlloc::runOnFunction (Function &F) {
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// Create each RegClass for the target machine and add it to the
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// RegClassList. This must be done before calling constructLiveRanges().
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for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
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RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
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MRI.getMachineRegClass (rc)));
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RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
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MRI.getMachineRegClass(rc)));
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LRI->constructLiveRanges(); // create LR info
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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@ -93,7 +93,7 @@ public:
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typedef std::map<const Function *, std::vector<AllocInfo> > SavedStateMapTy;
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inline PhyRegAlloc (const TargetMachine &TM_) :
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TM (TM_), MRI (TM.getRegInfo ()),
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TM (TM_), MRI (*TM.getRegInfo ()),
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NumOfRegClasses (MRI.getNumOfRegClasses ()) { }
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virtual ~PhyRegAlloc() { }
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@ -74,6 +74,15 @@ namespace {
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arrayType->getElementType() == Type::SByteTy);
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}
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unsigned findOptimalStorageSize(const TargetMachine &TM, const Type *Ty) {
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// All integer types smaller than ints promote to 4 byte integers.
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if (Ty->isIntegral() && Ty->getPrimitiveSize() < 4)
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return 4;
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return TM.getTargetData().getTypeSize(Ty);
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}
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inline const std::string
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TypeToDataDirective(const Type* type) {
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switch(type->getPrimitiveID())
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@ -111,7 +120,7 @@ namespace {
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return 1 + CVA->getNumOperands();
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}
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return target.findOptimalStorageSize(CV->getType());
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return findOptimalStorageSize(target, CV->getType());
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}
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/// Align data larger than one L1 cache line on L1 cache line boundaries.
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@ -132,7 +141,7 @@ namespace {
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///
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inline unsigned int
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TypeToAlignment(const Type* type, const TargetMachine& target) {
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return SizeToAlignment(target.findOptimalStorageSize(type), target);
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return SizeToAlignment(findOptimalStorageSize(target, type), target);
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}
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/// Get the size of the constant and then use SizeToAlignment.
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@ -580,9 +589,9 @@ SparcV9AsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
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inline bool
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SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
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unsigned int opNum) {
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if (Target.getInstrInfo().isLoad(MI->getOpcode()))
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if (Target.getInstrInfo()->isLoad(MI->getOpcode()))
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return (opNum == 0);
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else if (Target.getInstrInfo().isStore(MI->getOpcode()))
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else if (Target.getInstrInfo()->isStore(MI->getOpcode()))
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return (opNum == 1);
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else
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return false;
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@ -639,11 +648,11 @@ SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
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{
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int regNum = (int)mop.getReg();
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if (regNum == Target.getRegInfo().getInvalidRegNum()) {
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if (regNum == Target.getRegInfo()->getInvalidRegNum()) {
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// better to print code with NULL registers than to die
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toAsm << "<NULL VALUE>";
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} else {
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toAsm << "%" << Target.getRegInfo().getUnifiedRegName(regNum);
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toAsm << "%" << Target.getRegInfo()->getUnifiedRegName(regNum);
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}
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break;
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}
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@ -693,10 +702,10 @@ SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
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void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
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if (Target.getInstrInfo()->isDummyPhiInstr(Opcode))
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return; // IGNORE PHI NODES
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toAsm << "\t" << Target.getInstrInfo().getName(Opcode) << "\t";
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toAsm << "\t" << Target.getInstrInfo()->getName(Opcode) << "\t";
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unsigned Mask = getOperandMask(Opcode);
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@ -770,7 +779,7 @@ void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
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Target) << "\n";
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toAsm << "\t.type\t" << getID(GV) << ",#object\n";
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toAsm << "\t.reserve\t" << getID(GV) << ","
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<< Target.findOptimalStorageSize(GV->getType()->getElementType())
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<< findOptimalStorageSize(Target, GV->getType()->getElementType())
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<< "\n";
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}
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}
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@ -474,7 +474,7 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) {
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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MachineInstr &MI) {
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const TargetRegInfo &RI = TM.getRegInfo();
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const TargetRegInfo &RI = *TM.getRegInfo();
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unsigned regClass, regType = RI.getRegType(fakeReg);
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// At least map fakeReg into its class
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fakeReg = RI.getClassRegNum(fakeReg, regClass);
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@ -656,7 +656,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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unsigned realRegByClass = getRealRegNum(fakeReg, MI);
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DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
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<< realRegByClass << " (LLC: "
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<< TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n");
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<< TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
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rv = realRegByClass;
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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@ -72,22 +72,22 @@ public:
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// (generally FP or SP)
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//
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virtual int getIncomingArgBaseRegNum() const {
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return (int) target.getRegInfo().getFramePointer();
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return (int) target.getRegInfo()->getFramePointer();
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}
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virtual int getOutgoingArgBaseRegNum() const {
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return (int) target.getRegInfo().getStackPointer();
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return (int) target.getRegInfo()->getStackPointer();
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}
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virtual int getOptionalOutgoingArgBaseRegNum() const {
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return (int) target.getRegInfo().getStackPointer();
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return (int) target.getRegInfo()->getStackPointer();
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}
|
||||
virtual int getAutomaticVarBaseRegNum() const {
|
||||
return (int) target.getRegInfo().getFramePointer();
|
||||
return (int) target.getRegInfo()->getFramePointer();
|
||||
}
|
||||
virtual int getRegSpillAreaBaseRegNum() const {
|
||||
return (int) target.getRegInfo().getFramePointer();
|
||||
return (int) target.getRegInfo()->getFramePointer();
|
||||
}
|
||||
virtual int getDynamicAreaBaseRegNum() const {
|
||||
return (int) target.getRegInfo().getStackPointer();
|
||||
return (int) target.getRegInfo()->getStackPointer();
|
||||
}
|
||||
|
||||
virtual int getIncomingArgOffset(MachineFunction& mcInfo,
|
||||
|
@ -174,8 +174,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
|
||||
} else {
|
||||
// unsigned or small signed value that fits in simm13 field of OR
|
||||
assert(smallNegValue || (C & ~MAXSIMM) == 0);
|
||||
miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
|
||||
.getZeroRegNum())
|
||||
miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()->getZeroRegNum())
|
||||
.addSImm(sC).addRegDef(dest);
|
||||
}
|
||||
mvec.push_back(miOR);
|
||||
@ -588,7 +587,7 @@ SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
|
||||
mvec, mcfi);
|
||||
}
|
||||
|
||||
unsigned FPReg = target.getRegInfo().getFramePointer();
|
||||
unsigned FPReg = target.getRegInfo()->getFramePointer();
|
||||
unsigned StoreOpcode = ChooseStoreInstruction(storeType);
|
||||
StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
|
||||
mvec.push_back(BuildMI(StoreOpcode, 3)
|
||||
@ -633,7 +632,7 @@ SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
|
||||
//
|
||||
int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
|
||||
|
||||
unsigned FPReg = target.getRegInfo().getFramePointer();
|
||||
unsigned FPReg = target.getRegInfo()->getFramePointer();
|
||||
|
||||
// Store instruction stores `val' to [%fp+offset].
|
||||
// The store opCode is based only the source value being copied.
|
||||
@ -699,8 +698,8 @@ SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
|
||||
if (loadConstantToReg) {
|
||||
// `src' is constant and cannot fit in immed field for the ADD
|
||||
// Insert instructions to "load" the constant into a register
|
||||
target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
|
||||
mvec, mcfi);
|
||||
target.getInstrInfo()->CreateCodeToLoadConst(target, F, src, dest,
|
||||
mvec, mcfi);
|
||||
} else {
|
||||
// Create a reg-to-reg copy instruction for the given type:
|
||||
// -- For FP values, create a FMOVS or FMOVD instruction
|
||||
|
@ -592,12 +592,12 @@ CreateCodeToConvertFloatToInt(const TargetMachine& target,
|
||||
castDestType));
|
||||
|
||||
// Create the fpreg-to-intreg copy code
|
||||
target.getInstrInfo().CreateCodeToCopyFloatToInt(target, F, destForCast,
|
||||
target.getInstrInfo()->CreateCodeToCopyFloatToInt(target, F, destForCast,
|
||||
fpToIntCopyDest, mvec, mcfi);
|
||||
|
||||
// Create the uint64_t to uint32_t conversion, if needed
|
||||
if (destI->getType() == Type::UIntTy)
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI,
|
||||
/*numLowBits*/ 32, mvec, mcfi);
|
||||
}
|
||||
@ -743,7 +743,7 @@ static inline MachineInstr*
|
||||
CreateIntNegInstruction(const TargetMachine& target,
|
||||
Value* vreg)
|
||||
{
|
||||
return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo().getZeroRegNum())
|
||||
return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo()->getZeroRegNum())
|
||||
.addReg(vreg).addRegDef(vreg);
|
||||
}
|
||||
|
||||
@ -793,7 +793,7 @@ CreateShiftInstructions(const TargetMachine& target,
|
||||
if (shiftDest != destVal) {
|
||||
// extend the sign-bit of the result into all upper bits of dest
|
||||
assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateSignExtensionInstructions(target, F, shiftDest, destVal,
|
||||
8*opSize, mvec, mcfi);
|
||||
}
|
||||
@ -811,7 +811,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
|
||||
MachineCodeForInstruction& mcfi)
|
||||
{
|
||||
/* Use max. multiply cost, viz., cost of MULX */
|
||||
unsigned cost = target.getInstrInfo().minLatency(V9::MULXr);
|
||||
unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr);
|
||||
unsigned firstNewInstr = mvec.size();
|
||||
|
||||
Value* constOp = rval;
|
||||
@ -826,7 +826,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
|
||||
|
||||
if (resultType->isInteger() || isa<PointerType>(resultType)) {
|
||||
bool isValidConst;
|
||||
int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target,
|
||||
int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target,
|
||||
constOp, constOp->getType(), isValidConst);
|
||||
if (isValidConst) {
|
||||
unsigned pow;
|
||||
@ -837,8 +837,8 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
|
||||
}
|
||||
|
||||
if (C == 0 || C == 1) {
|
||||
cost = target.getInstrInfo().minLatency(V9::ADDr);
|
||||
unsigned Zero = target.getRegInfo().getZeroRegNum();
|
||||
cost = target.getInstrInfo()->minLatency(V9::ADDr);
|
||||
unsigned Zero = target.getRegInfo()->getZeroRegNum();
|
||||
MachineInstr* M;
|
||||
if (C == 0)
|
||||
M =BuildMI(V9::ADDr,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
|
||||
@ -873,7 +873,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
|
||||
if (firstNewInstr < mvec.size()) {
|
||||
cost = 0;
|
||||
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
|
||||
cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode());
|
||||
cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode());
|
||||
}
|
||||
|
||||
return cost;
|
||||
@ -897,7 +897,7 @@ CreateCheapestMulConstInstruction(const TargetMachine &target,
|
||||
Constant* P = ConstantExpr::get(Instruction::Mul,
|
||||
cast<Constant>(lval),
|
||||
cast<Constant>(rval));
|
||||
target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
|
||||
target.getInstrInfo()->CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
|
||||
}
|
||||
else if (isa<Constant>(rval)) // rval is constant, but not lval
|
||||
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
|
||||
@ -969,7 +969,7 @@ CreateDivConstInstruction(TargetMachine &target,
|
||||
return;
|
||||
|
||||
Instruction* destVal = instrNode->getInstruction();
|
||||
unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
|
||||
unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
|
||||
|
||||
// Cases worth optimizing are:
|
||||
// (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
|
||||
@ -980,7 +980,7 @@ CreateDivConstInstruction(TargetMachine &target,
|
||||
if (resultType->isInteger()) {
|
||||
unsigned pow;
|
||||
bool isValidConst;
|
||||
int64_t C = (int64_t) target.getInstrInfo().ConvertConstantToIntType(target,
|
||||
int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target,
|
||||
constOp, constOp->getType(), isValidConst);
|
||||
if (isValidConst) {
|
||||
bool needNeg = false;
|
||||
@ -1089,13 +1089,13 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
|
||||
// compile time if the total size is a known constant.
|
||||
if (isa<Constant>(numElementsVal)) {
|
||||
bool isValid;
|
||||
int64_t numElem = (int64_t) target.getInstrInfo().
|
||||
int64_t numElem = (int64_t) target.getInstrInfo()->
|
||||
ConvertConstantToIntType(target, numElementsVal,
|
||||
numElementsVal->getType(), isValid);
|
||||
assert(isValid && "Unexpectedly large array dimension in alloca!");
|
||||
int64_t total = numElem * tsize;
|
||||
if (int extra= total % target.getFrameInfo().getStackFrameSizeAlignment())
|
||||
total += target.getFrameInfo().getStackFrameSizeAlignment() - extra;
|
||||
if (int extra= total % target.getFrameInfo()->getStackFrameSizeAlignment())
|
||||
total += target.getFrameInfo()->getStackFrameSizeAlignment() - extra;
|
||||
totalSizeVal = ConstantSInt::get(Type::IntTy, total);
|
||||
} else {
|
||||
// The size is not a constant. Generate code to compute it and
|
||||
@ -1133,10 +1133,10 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
|
||||
bool growUp;
|
||||
ConstantSInt* dynamicAreaOffset =
|
||||
ConstantSInt::get(Type::IntTy,
|
||||
target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
|
||||
target.getFrameInfo()->getDynamicAreaOffset(mcInfo,growUp));
|
||||
assert(! growUp && "Has SPARC v9 stack frame convention changed?");
|
||||
|
||||
unsigned SPReg = target.getRegInfo().getStackPointer();
|
||||
unsigned SPReg = target.getRegInfo()->getStackPointer();
|
||||
|
||||
// Instruction 2: sub %sp, totalSizeVal -> %sp
|
||||
getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
|
||||
@ -1180,8 +1180,8 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
|
||||
paddedSize,
|
||||
tsize * numElements);
|
||||
|
||||
if (((int)paddedSize) > 8 * target.getFrameInfo().getSizeOfEachArgOnStack() ||
|
||||
! target.getInstrInfo().constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
|
||||
if (((int)paddedSize) > 8 * target.getFrameInfo()->getSizeOfEachArgOnStack() ||
|
||||
! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
|
||||
CreateCodeForVariableSizeAlloca(target, result, tsize,
|
||||
ConstantSInt::get(Type::IntTy,numElements),
|
||||
getMvec);
|
||||
@ -1196,7 +1196,7 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
|
||||
ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
|
||||
|
||||
// Instruction 1: add %fp, offsetFromFP -> result
|
||||
unsigned FPReg = target.getRegInfo().getFramePointer();
|
||||
unsigned FPReg = target.getRegInfo()->getFramePointer();
|
||||
getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal)
|
||||
.addRegDef(result));
|
||||
}
|
||||
@ -1408,9 +1408,9 @@ static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
|
||||
bool ignore;
|
||||
Function* func = cast<Function>(callInstr.getParent()->getParent());
|
||||
int numFixedArgs = func->getFunctionType()->getNumParams();
|
||||
int fpReg = target.getFrameInfo().getIncomingArgBaseRegNum();
|
||||
int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
|
||||
int firstVarArgOff = numFixedArgs * argSize + target.getFrameInfo().
|
||||
int fpReg = target.getFrameInfo()->getIncomingArgBaseRegNum();
|
||||
int argSize = target.getFrameInfo()->getSizeOfEachArgOnStack();
|
||||
int firstVarArgOff = numFixedArgs * argSize + target.getFrameInfo()->
|
||||
getFirstIncomingArgOffset(MachineFunction::get(func), ignore);
|
||||
mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).
|
||||
addRegDef(&callInstr));
|
||||
@ -1423,7 +1423,7 @@ static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
|
||||
case Intrinsic::vacopy:
|
||||
// Simple copy of current va_list (arg1) to new va_list (result)
|
||||
mvec.push_back(BuildMI(V9::ORr, 3).
|
||||
addMReg(target.getRegInfo().getZeroRegNum()).
|
||||
addMReg(target.getRegInfo()->getZeroRegNum()).
|
||||
addReg(callInstr.getOperand(1)).
|
||||
addRegDef(&callInstr));
|
||||
return true;
|
||||
@ -1539,7 +1539,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
MachineInstr* retMI =
|
||||
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
|
||||
.addMReg(target.getRegInfo().getZeroRegNum(), MachineOperand::Def);
|
||||
.addMReg(target.getRegInfo()->getZeroRegNum(), MachineOperand::Def);
|
||||
|
||||
// If there is a value to return, we need to:
|
||||
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
|
||||
@ -1549,7 +1549,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
//
|
||||
if (retVal != NULL) {
|
||||
const SparcV9RegInfo& regInfo =
|
||||
(SparcV9RegInfo&) target.getRegInfo();
|
||||
(SparcV9RegInfo&) *target.getRegInfo();
|
||||
const Type* retType = retVal->getType();
|
||||
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
|
||||
unsigned retRegNum = (retType->isFloatingPoint()
|
||||
@ -1567,7 +1567,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
retValToUse = new TmpInstruction(mcfi, retVal);
|
||||
|
||||
// sign-extend retVal and put the result in the temporary reg.
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
target.getInstrInfo()->CreateSignExtensionInstructions
|
||||
(target, returnInstr->getParent()->getParent(),
|
||||
retVal, retValToUse, 8*retSize, mvec, mcfi);
|
||||
}
|
||||
@ -1637,7 +1637,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
if ((constVal->getType()->isInteger()
|
||||
|| isa<PointerType>(constVal->getType()))
|
||||
&& target.getInstrInfo().ConvertConstantToIntType(target,
|
||||
&& target.getInstrInfo()->ConvertConstantToIntType(target,
|
||||
constVal, constVal->getType(), isValidConst) == 0
|
||||
&& isValidConst)
|
||||
{
|
||||
@ -1747,7 +1747,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
Instruction* notI = subtreeRoot->getInstruction();
|
||||
Value* notArg = BinaryOperator::getNotArgument(
|
||||
cast<BinaryOperator>(subtreeRoot->getInstruction()));
|
||||
unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
|
||||
unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
|
||||
|
||||
// Unconditionally set register to 0
|
||||
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(notI));
|
||||
@ -1765,7 +1765,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
{ // First find the unary operand. It may be left or right, usually right.
|
||||
Value* notArg = BinaryOperator::getNotArgument(
|
||||
cast<BinaryOperator>(subtreeRoot->getInstruction()));
|
||||
unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
|
||||
unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
|
||||
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(notArg).addMReg(ZeroReg)
|
||||
.addRegDef(subtreeRoot->getValue()));
|
||||
break;
|
||||
@ -1889,15 +1889,15 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
? new TmpInstruction(mcfi, destType, opVal)
|
||||
: destI);
|
||||
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
target.getInstrInfo()->CreateSignExtensionInstructions
|
||||
(target, currentFunc,opVal,signExtDest,extSourceInBits,mvec,mcfi);
|
||||
|
||||
if (signAndZeroExtend)
|
||||
target.getInstrInfo().CreateZeroExtensionInstructions
|
||||
target.getInstrInfo()->CreateZeroExtensionInstructions
|
||||
(target, currentFunc, signExtDest, destI, 8*destSize, mvec, mcfi);
|
||||
}
|
||||
else if (zeroExtendOnly) {
|
||||
target.getInstrInfo().CreateZeroExtensionInstructions
|
||||
target.getInstrInfo()->CreateZeroExtensionInstructions
|
||||
(target, currentFunc, opVal, destI, extSourceInBits, mvec, mcfi);
|
||||
}
|
||||
else
|
||||
@ -1955,7 +1955,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
MachineCodeForInstruction::get(dest);
|
||||
srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest);
|
||||
|
||||
target.getInstrInfo().CreateCodeToCopyIntToFloat(target,
|
||||
target.getInstrInfo()->CreateCodeToCopyIntToFloat(target,
|
||||
dest->getParent()->getParent(),
|
||||
leftVal, cast<Instruction>(srcForCast),
|
||||
mvec, destMCFI);
|
||||
@ -2067,12 +2067,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(divI);
|
||||
divOp1ToUse = new TmpInstruction(mcfi, divOp1);
|
||||
divOp2ToUse = new TmpInstruction(mcfi, divOp2);
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateSignExtensionInstructions(target,
|
||||
divI->getParent()->getParent(),
|
||||
divOp1, divOp1ToUse,
|
||||
8*opSize, mvec, mcfi);
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateSignExtensionInstructions(target,
|
||||
divI->getParent()->getParent(),
|
||||
divOp2, divOp2ToUse,
|
||||
@ -2109,7 +2109,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
|
||||
if (opSize < 8) {
|
||||
divOpToUse = new TmpInstruction(mcfi, divOp2);
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateSignExtensionInstructions(target,
|
||||
remI->getParent()->getParent(),
|
||||
divOp2, divOpToUse,
|
||||
@ -2251,7 +2251,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
|
||||
if ((constVal->getType()->isInteger()
|
||||
|| isa<PointerType>(constVal->getType()))
|
||||
&& target.getInstrInfo().ConvertConstantToIntType(target,
|
||||
&& target.getInstrInfo()->ConvertConstantToIntType(target,
|
||||
constVal, constVal->getType(), isValidConst) == 0
|
||||
&& isValidConst)
|
||||
{
|
||||
@ -2328,10 +2328,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
rightOpToUse = new TmpInstruction(mcfi, rightVal);
|
||||
|
||||
// sign-extend each operand and put the result in the temporary reg.
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
target.getInstrInfo()->CreateSignExtensionInstructions
|
||||
(target, setCCInstr->getParent()->getParent(),
|
||||
leftVal, leftOpToUse, 8*opSize, mvec, mcfi);
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
target.getInstrInfo()->CreateSignExtensionInstructions
|
||||
(target, setCCInstr->getParent()->getParent(),
|
||||
rightVal, rightOpToUse, 8*opSize, mvec, mcfi);
|
||||
}
|
||||
@ -2342,8 +2342,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
mvec.push_back(BuildMI(V9::SUBccr, 4)
|
||||
.addReg(leftOpToUse)
|
||||
.addReg(rightOpToUse)
|
||||
.addMReg(target.getRegInfo()
|
||||
.getZeroRegNum(), MachineOperand::Def)
|
||||
.addMReg(target.getRegInfo()->
|
||||
getZeroRegNum(), MachineOperand::Def)
|
||||
.addCCReg(tmpForCC, MachineOperand::Def));
|
||||
} else {
|
||||
// FP condition: dest of FCMP should be some FCCn register
|
||||
@ -2456,8 +2456,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
MachineCodeForInstruction& mcfi =
|
||||
MachineCodeForInstruction::get(callInstr);
|
||||
const SparcV9RegInfo& regInfo =
|
||||
(SparcV9RegInfo&) target.getRegInfo();
|
||||
const TargetFrameInfo& frameInfo = target.getFrameInfo();
|
||||
(SparcV9RegInfo&) *target.getRegInfo();
|
||||
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
|
||||
|
||||
// Create hidden virtual register for return address with type void*
|
||||
TmpInstruction* retAddrReg =
|
||||
@ -2506,7 +2506,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
TmpInstruction* argExtend = new TmpInstruction(mcfi, argVal);
|
||||
|
||||
// sign-extend argVal and put the result in the temporary reg.
|
||||
target.getInstrInfo().CreateSignExtensionInstructions
|
||||
target.getInstrInfo()->CreateSignExtensionInstructions
|
||||
(target, currentFunc, argVal, argExtend,
|
||||
8*argSize, mvec, mcfi);
|
||||
|
||||
@ -2787,7 +2787,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
Instruction* vaNextI = subtreeRoot->getInstruction();
|
||||
assert(target.getTargetData().getTypeSize(vaNextI->getType()) <= 8 &&
|
||||
"We assumed that all LLVM parameter types <= 8 bytes!");
|
||||
int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
|
||||
int argSize = target.getFrameInfo()->getSizeOfEachArgOnStack();
|
||||
mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaNextI->getOperand(0)).
|
||||
addSImm(argSize).addRegDef(vaNextI));
|
||||
break;
|
||||
@ -2826,7 +2826,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
||||
else {
|
||||
std::vector<MachineInstr*> minstrVec;
|
||||
Instruction* instr = subtreeRoot->getInstruction();
|
||||
target.getInstrInfo().
|
||||
target.getInstrInfo()->
|
||||
CreateCopyInstructionsByType(target,
|
||||
instr->getParent()->getParent(),
|
||||
instr->getOperand(forwardOperandNum),
|
||||
|
@ -31,7 +31,7 @@ DeleteInstruction(MachineBasicBlock& mvec,
|
||||
const TargetMachine& target) {
|
||||
// Check if this instruction is in a delay slot of its predecessor.
|
||||
if (BBI != mvec.begin()) {
|
||||
const TargetInstrInfo& mii = target.getInstrInfo();
|
||||
const TargetInstrInfo& mii = *target.getInstrInfo();
|
||||
MachineBasicBlock::iterator predMI = prior(BBI);
|
||||
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
|
||||
// This instruction is in a delay slot of its predecessor, so
|
||||
@ -83,7 +83,7 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
|
||||
return (// either operand otherOp is register %g0
|
||||
(MI->getOperand(otherOp).hasAllocatedReg() &&
|
||||
MI->getOperand(otherOp).getReg() ==
|
||||
target.getRegInfo().getZeroRegNum()) ||
|
||||
target.getRegInfo()->getZeroRegNum()) ||
|
||||
|
||||
// or operand otherOp == 0
|
||||
(MI->getOperand(otherOp).getType()
|
||||
|
@ -41,7 +41,7 @@ namespace {
|
||||
|
||||
public:
|
||||
PreSelection(const TargetMachine &T)
|
||||
: instrInfo(T.getInstrInfo()) {}
|
||||
: instrInfo(*T.getInstrInfo()) {}
|
||||
|
||||
// runOnFunction - apply this pass to each Function
|
||||
bool runOnFunction(Function &F) {
|
||||
|
@ -52,7 +52,7 @@ namespace {
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
static unsigned getStaticStackSize (MachineFunction &MF) {
|
||||
const TargetFrameInfo& frameInfo = MF.getTarget().getFrameInfo();
|
||||
const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo();
|
||||
|
||||
unsigned staticStackSize = MF.getInfo()->getStaticStackSize();
|
||||
|
||||
@ -69,7 +69,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
|
||||
{
|
||||
std::vector<MachineInstr*> mvec;
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const TargetFrameInfo& frameInfo = TM.getFrameInfo();
|
||||
const TargetFrameInfo& frameInfo = *TM.getFrameInfo();
|
||||
|
||||
// The second operand is the stack size. If it does not fit in the
|
||||
// immediate field, we have to use a free register to hold the size.
|
||||
@ -77,8 +77,8 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
|
||||
//
|
||||
unsigned staticStackSize = getStaticStackSize (MF);
|
||||
int32_t C = - (int) staticStackSize;
|
||||
int SP = TM.getRegInfo().getStackPointer();
|
||||
if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
|
||||
int SP = TM.getRegInfo()->getStackPointer();
|
||||
if (TM.getInstrInfo()->constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
|
||||
mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
|
||||
.addMReg(SP, MachineOperand::Def));
|
||||
} else {
|
||||
@ -87,8 +87,8 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
|
||||
// local (%l) and in (%i) registers cannot be used before the SAVE!
|
||||
// Do this by creating a code sequence equivalent to:
|
||||
// SETSW -(stackSize), %g1
|
||||
int uregNum = TM.getRegInfo().getUnifiedRegNum(
|
||||
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
|
||||
int uregNum = TM.getRegInfo()->getUnifiedRegNum(
|
||||
TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
|
||||
SparcV9IntRegClass::g1);
|
||||
|
||||
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
|
||||
@ -120,15 +120,16 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
|
||||
//
|
||||
if (MF.getFunction()->getFunctionType()->isVarArg()) {
|
||||
int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
|
||||
int numArgRegs = TM.getRegInfo().getNumOfIntArgRegs();
|
||||
int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs();
|
||||
if (numFixedArgs < numArgRegs) {
|
||||
const TargetFrameInfo &FI = *TM.getFrameInfo();
|
||||
bool ignore;
|
||||
int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
|
||||
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
|
||||
int firstArgReg = TM.getRegInfo()->getUnifiedRegNum(
|
||||
TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
|
||||
SparcV9IntRegClass::i0);
|
||||
int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
|
||||
int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
|
||||
int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);
|
||||
int fpReg = FI.getIncomingArgBaseRegNum();
|
||||
int argSize = FI.getSizeOfEachArgOnStack();
|
||||
int firstArgOffset= FI.getFirstIncomingArgOffset(MF,ignore);
|
||||
int nextArgOffset = firstArgOffset + numFixedArgs * argSize;
|
||||
|
||||
for (int i=numFixedArgs; i < numArgRegs; ++i) {
|
||||
@ -145,7 +146,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
|
||||
void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
|
||||
{
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const TargetInstrInfo &MII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &MII = *TM.getInstrInfo();
|
||||
|
||||
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
||||
MachineBasicBlock &MBB = *I;
|
||||
@ -153,7 +154,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
|
||||
const Instruction *TermInst = (Instruction*)BB.getTerminator();
|
||||
if (TermInst->getOpcode() == Instruction::Ret)
|
||||
{
|
||||
int ZR = TM.getRegInfo().getZeroRegNum();
|
||||
int ZR = TM.getRegInfo()->getZeroRegNum();
|
||||
MachineInstr *Restore =
|
||||
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
|
||||
.addMReg(ZR, MachineOperand::Def);
|
||||
|
@ -314,7 +314,7 @@ unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
|
||||
void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
|
||||
LiveRangeInfo& LRI) const {
|
||||
|
||||
assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
|
||||
assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
|
||||
|
||||
// return address is always mapped to i7 so set it immediately
|
||||
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
|
||||
@ -482,7 +482,7 @@ void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
|
||||
// Now the arg is coming on stack. Since the LR received a register,
|
||||
// we just have to load the arg on stack into that register
|
||||
//
|
||||
const TargetFrameInfo& frameInfo = target.getFrameInfo();
|
||||
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
|
||||
int offsetFromFP =
|
||||
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
|
||||
argNo);
|
||||
@ -540,7 +540,7 @@ void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
|
||||
// since this method is called before any other method that makes
|
||||
// uses of the stack pos of the LR (e.g., updateMachineInstr)
|
||||
//
|
||||
const TargetFrameInfo& frameInfo = target.getFrameInfo();
|
||||
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
|
||||
int offsetFromFP =
|
||||
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
|
||||
argNo);
|
||||
@ -572,7 +572,7 @@ void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
|
||||
//---------------------------------------------------------------------------
|
||||
void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
|
||||
LiveRangeInfo& LRI) const {
|
||||
assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
|
||||
assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
|
||||
|
||||
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
||||
|
||||
@ -641,7 +641,7 @@ void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
|
||||
void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
|
||||
LiveRangeInfo& LRI) const {
|
||||
|
||||
assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
|
||||
assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
|
||||
|
||||
suggestReg4RetAddr(RetMI, LRI);
|
||||
|
||||
@ -764,7 +764,7 @@ SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
|
||||
// Use the register allocator, PRA, to find an unused reg. at this MI.
|
||||
//
|
||||
if (RegType != IntCCRegType) // does not use offset below
|
||||
if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
|
||||
if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
|
||||
#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
|
||||
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
|
||||
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
|
||||
@ -779,21 +779,21 @@ SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
|
||||
|
||||
switch (RegType) {
|
||||
case IntRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::STXi, Offset))
|
||||
MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
|
||||
else
|
||||
MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
|
||||
break;
|
||||
|
||||
case FPSingleRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::STFi, Offset))
|
||||
MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
|
||||
else
|
||||
MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
|
||||
break;
|
||||
|
||||
case FPDoubleRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::STDFi, Offset))
|
||||
MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
|
||||
else
|
||||
MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
|
||||
@ -815,7 +815,7 @@ SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
|
||||
case FloatCCRegType: {
|
||||
unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
|
||||
SparcV9SpecialRegClass::fsr);
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::STXFSRi, Offset))
|
||||
MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
|
||||
else
|
||||
MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
|
||||
@ -850,7 +850,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
// Use the register allocator, PRA, to find an unused reg. at this MI.
|
||||
//
|
||||
if (RegType != IntCCRegType) // does not use offset below
|
||||
if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
|
||||
if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
|
||||
#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
|
||||
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
|
||||
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
|
||||
@ -865,7 +865,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
|
||||
switch (RegType) {
|
||||
case IntRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset))
|
||||
MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
|
||||
.addMReg(DestReg, MachineOperand::Def);
|
||||
else
|
||||
@ -874,7 +874,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
break;
|
||||
|
||||
case FPSingleRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::LDFi, Offset))
|
||||
MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
|
||||
.addMReg(DestReg, MachineOperand::Def);
|
||||
else
|
||||
@ -883,7 +883,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
break;
|
||||
|
||||
case FPDoubleRegType:
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::LDDFi, Offset))
|
||||
MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
|
||||
.addMReg(DestReg, MachineOperand::Def);
|
||||
else
|
||||
@ -906,7 +906,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
case FloatCCRegType: {
|
||||
unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
|
||||
SparcV9SpecialRegClass::fsr);
|
||||
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
|
||||
if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXFSRi, Offset))
|
||||
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
|
||||
.addMReg(fsrRegNum, MachineOperand::UseAndDef);
|
||||
else
|
||||
|
@ -34,10 +34,10 @@ class SparcV9TargetMachine : public TargetMachine {
|
||||
public:
|
||||
SparcV9TargetMachine(IntrinsicLowering *IL);
|
||||
|
||||
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
|
||||
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
|
||||
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
|
||||
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
|
||||
virtual const TargetInstrInfo *getInstrInfo() const { return &instrInfo; }
|
||||
virtual const TargetSchedInfo *getSchedInfo() const { return &schedInfo; }
|
||||
virtual const TargetRegInfo *getRegInfo() const { return ®Info; }
|
||||
virtual const TargetFrameInfo *getFrameInfo() const { return &frameInfo; }
|
||||
virtual TargetJITInfo *getJITInfo() { return &jitInfo; }
|
||||
virtual const MRegisterInfo *getRegisterInfo() const {
|
||||
return &instrInfo.getRegisterInfo();
|
||||
|
@ -177,7 +177,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) {
|
||||
/// transforming FP instructions into their stack form.
|
||||
///
|
||||
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
|
||||
const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
|
||||
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
||||
bool Changed = false;
|
||||
MBB = &BB;
|
||||
|
||||
|
@ -638,7 +638,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
|
||||
/// the current one.
|
||||
///
|
||||
void ISel::SelectPHINodes() {
|
||||
const TargetInstrInfo &TII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const Function &LF = *F->getFunction(); // The LLVM function...
|
||||
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
|
||||
const BasicBlock *BB = I;
|
||||
|
@ -456,7 +456,7 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
|
||||
|
||||
bool Changed = false;
|
||||
|
||||
const TargetInstrInfo &TII = MBB.getParent()->getTarget().getInstrInfo();
|
||||
const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
|
||||
|
||||
// Scan the operands of this instruction. If any operands are
|
||||
// register-register copies, replace the operand with the source.
|
||||
|
@ -623,7 +623,7 @@ bool Printer::printImplDefsAfter(const TargetInstrDescriptor &Desc,
|
||||
///
|
||||
void Printer::printMachineInstruction(const MachineInstr *MI) {
|
||||
unsigned Opcode = MI->getOpcode();
|
||||
const TargetInstrInfo &TII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
||||
|
||||
++EmittedInsts;
|
||||
@ -921,7 +921,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
|
||||
MI->getOpcode() == X86::FILD64m ||
|
||||
MI->getOpcode() == X86::FISTP64m) {
|
||||
GasBugWorkaroundEmitter gwe(O);
|
||||
X86::emitInstruction(gwe, (X86InstrInfo&)TM.getInstrInfo(), *MI);
|
||||
X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
|
||||
}
|
||||
|
||||
O << TII.getName(MI->getOpcode()) << " ";
|
||||
|
@ -623,7 +623,7 @@ bool Printer::printImplDefsAfter(const TargetInstrDescriptor &Desc,
|
||||
///
|
||||
void Printer::printMachineInstruction(const MachineInstr *MI) {
|
||||
unsigned Opcode = MI->getOpcode();
|
||||
const TargetInstrInfo &TII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
||||
|
||||
++EmittedInsts;
|
||||
@ -921,7 +921,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
|
||||
MI->getOpcode() == X86::FILD64m ||
|
||||
MI->getOpcode() == X86::FISTP64m) {
|
||||
GasBugWorkaroundEmitter gwe(O);
|
||||
X86::emitInstruction(gwe, (X86InstrInfo&)TM.getInstrInfo(), *MI);
|
||||
X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
|
||||
}
|
||||
|
||||
O << TII.getName(MI->getOpcode()) << " ";
|
||||
|
@ -228,7 +228,7 @@ bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
}
|
||||
|
||||
bool Emitter::runOnMachineFunction(MachineFunction &MF) {
|
||||
II = &((X86TargetMachine&)MF.getTarget()).getInstrInfo();
|
||||
II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
|
||||
|
||||
MCE.startFunction(MF);
|
||||
MCE.emitConstantPool(MF.getConstantPool());
|
||||
|
@ -177,7 +177,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) {
|
||||
/// transforming FP instructions into their stack form.
|
||||
///
|
||||
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
|
||||
const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
|
||||
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
|
||||
bool Changed = false;
|
||||
MBB = &BB;
|
||||
|
||||
|
@ -638,7 +638,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
|
||||
/// the current one.
|
||||
///
|
||||
void ISel::SelectPHINodes() {
|
||||
const TargetInstrInfo &TII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const Function &LF = *F->getFunction(); // The LLVM function...
|
||||
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
|
||||
const BasicBlock *BB = I;
|
||||
|
@ -456,7 +456,7 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
|
||||
|
||||
bool Changed = false;
|
||||
|
||||
const TargetInstrInfo &TII = MBB.getParent()->getTarget().getInstrInfo();
|
||||
const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
|
||||
|
||||
// Scan the operands of this instruction. If any operands are
|
||||
// register-register copies, replace the operand with the source.
|
||||
|
@ -350,7 +350,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
// We need to keep the stack aligned properly. To do this, we round the
|
||||
// amount of space needed for the outgoing arguments up to the next
|
||||
// alignment boundary.
|
||||
unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
|
||||
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
||||
Amount = (Amount+Align-1)/Align*Align;
|
||||
|
||||
MachineInstr *New;
|
||||
@ -450,7 +450,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
|
||||
// Round the size to a multiple of the alignment (don't forget the 4 byte
|
||||
// offset though).
|
||||
unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
|
||||
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
||||
NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
|
||||
}
|
||||
|
||||
|
@ -557,7 +557,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
|
||||
/// the current one.
|
||||
///
|
||||
void ISel::SelectPHINodes() {
|
||||
const TargetInstrInfo &TII = TM.getInstrInfo();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const Function &LF = *F->getFunction(); // The LLVM function...
|
||||
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
|
||||
const BasicBlock *BB = I;
|
||||
|
@ -30,17 +30,13 @@ class X86TargetMachine : public TargetMachine {
|
||||
public:
|
||||
X86TargetMachine(const Module &M, IntrinsicLowering *IL);
|
||||
|
||||
virtual const X86InstrInfo &getInstrInfo() const { return InstrInfo; }
|
||||
virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
|
||||
virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; }
|
||||
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
|
||||
virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
|
||||
virtual const MRegisterInfo *getRegisterInfo() const {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
|
||||
// deprecated interfaces
|
||||
virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
|
||||
virtual const TargetRegInfo &getRegInfo() const { abort(); }
|
||||
|
||||
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
|
||||
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
|
||||
/// actually outputting the machine code and resolving things like the address
|
||||
|
Loading…
Reference in New Issue
Block a user