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fix a subtle bug I introduced in my refactoring, where we stopped preferring
the i8 versions of instructions in some cases. In test6, we started generating: cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00] ## <MCInst #478 CMP64mi32 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> instead of: cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] ## <MCInst #479 CMP64mi8 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> Fix this and add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -839,14 +839,16 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
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def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
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def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
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def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
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}
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} // Constraints = "$src1 = $dst"
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@ -855,15 +857,17 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
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// NOTE: These are order specific, we want the mi8 forms to be listed
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// first so that they are slightly preferred to the mi forms.
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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@ -900,14 +904,16 @@ multiclass ArithBinOp_R<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#64rm : BinOpRM_R<BaseOpc2, mnemonic, Xi64, opnode>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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def #NAME#16ri8 : BinOpRI8_R<0x82, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_R<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_R<0x82, mnemonic, Xi64, opnode, RegMRM>;
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def #NAME#8ri : BinOpRI_R<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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def #NAME#16ri : BinOpRI_R<0x80, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri : BinOpRI_R<0x80, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri32: BinOpRI_R<0x80, mnemonic, Xi64, opnode, RegMRM>;
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def #NAME#16ri8 : BinOpRI8_R<0x82, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_R<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_R<0x82, mnemonic, Xi64, opnode, RegMRM>;
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}
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} // Constraints = "$src1 = $dst"
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@ -916,15 +922,17 @@ multiclass ArithBinOp_R<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
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// NOTE: These are order specific, we want the mi8 forms to be listed
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// first so that they are slightly preferred to the mi forms.
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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@ -960,14 +968,16 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
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def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
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def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
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def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
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}
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def #NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
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@ -975,15 +985,17 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
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def #NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
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// NOTE: These are order specific, we want the mi8 forms to be listed
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// first so that they are slightly preferred to the mi forms.
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def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
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def #NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
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def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
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def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
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def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
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def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
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def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
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