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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-06-05 03:44:29 +00:00
parent 76e9e838a1
commit d05b46115f
3 changed files with 7 additions and 9 deletions
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9
include/llvm/Target/TargetSchedule.td
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@ -1,10 +1,10 @@
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines the target-independent scheduling interfaces which should
@ -19,7 +19,7 @@
// all chip sets of the target. Each functional unit is treated as a resource
// during scheduling and has an affect instruction order based on availability
// during a time interval.
//
//
class FuncUnit;
//===----------------------------------------------------------------------===//
@ -84,7 +84,7 @@ class InstrItinClass<int ops = 1> {
def NoItinerary : InstrItinClass;
//===----------------------------------------------------------------------===//
// Instruction itinerary data - These values provide a runtime map of an
// Instruction itinerary data - These values provide a runtime map of an
// instruction itinerary class (name) to its itinerary data.
//
// OperandCycles are optional "cycle counts". They specify the cycle after
@ -119,6 +119,7 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
//
class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
list<InstrItinData> iid> {
int IssueWidth = 1;
list<FuncUnit> FU = fu;
list<Bypass> BP = bp;
list<InstrItinData> IID = iid;

5
lib/Target/X86/X86Schedule.td
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@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for X86
// Instruction Itinerary classes used for X86
def IIC_DEFAULT : InstrItinClass;
def IIC_ALU_MEM : InstrItinClass;
def IIC_ALU_NONMEM : InstrItinClass;
@ -459,6 +459,3 @@ def IIC_NOP : InstrItinClass;
def GenericItineraries : ProcessorItineraries<[], [], []>;
include "X86ScheduleAtom.td"

2
lib/Target/X86/X86ScheduleAtom.td
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@ -106,7 +106,7 @@ def AtomItineraries : ProcessorItineraries<
InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
// set
InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
// jcc
InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,