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Intel mode no longer uses %'s on registers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-01 05:56:51 +00:00
parent 99f2632b4b
commit d065c813c8
6 changed files with 7 additions and 7 deletions
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4
test/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*%AL' || \
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*%EAX'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*AL' || \
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*EAX'
; This testcase was compiling to:
;

2
test/CodeGen/X86/2005-12-03-IndirectTailCall.ll
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@ -1,5 +1,5 @@
; XFAIL: *
; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*%ecx'
; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*ecx'
declare int %putchar(int)
int %main(){

2
test/CodeGen/X86/fast-cc-merge-stack-adj.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'add %ESP, 8'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'add ESP, 8'
target triple = "i686-pc-linux-gnu"

2
test/CodeGen/X86/fast-cc-pass-in-regs.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov %EDX, 1'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov EDX, 1'
; check that fastcc is passing stuff in regs.
; Argument reg passing is disabled due to regalloc issues. FIXME!

2
test/CodeGen/X86/overlap-add.ll
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@ -6,7 +6,7 @@
; Check that the shift gets turned into an LEA.
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X'
; FIXME: We need live variable information about flags to do this xform safely. :(
; XFAIL: *

2
test/CodeGen/X86/overlap-shift.ll
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@ -6,7 +6,7 @@
; Check that the shift gets turned into an LEA.
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X'
%G = external global int