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Fix typos

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alp Toker 2014-06-19 19:41:26 +00:00
parent f21de942f3
commit d06976aba7
5 changed files with 8 additions and 8 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -7147,7 +7147,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
// thumb-2 environment, so there is no interworking required. As a result, we // thumb-2 environment, so there is no interworking required. As a result, we
// do not expect a veneer to be emitted by the linker, clobbering IP. // do not expect a veneer to be emitted by the linker, clobbering IP.
// //
// Each module recieves its own copy of __chkstk, so no import thunk is // Each module receives its own copy of __chkstk, so no import thunk is
// required, again, ensuring that IP is not clobbered. // required, again, ensuring that IP is not clobbered.
// //
// Finally, although some linkers may theoretically provide a trampoline for // Finally, although some linkers may theoretically provide a trampoline for

2
lib/Target/R600/AMDGPUIntrinsics.td
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@ -67,7 +67,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
def int_AMDGPU_barrier_global : Intrinsic<[], [], []>; def int_AMDGPU_barrier_global : Intrinsic<[], [], []>;
} }
// Legacy names for compatability. // Legacy names for compatibility.
let TargetPrefix = "AMDIL", isTarget = 1 in { let TargetPrefix = "AMDIL", isTarget = 1 in {
def int_AMDIL_abs : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; def int_AMDIL_abs : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_AMDIL_fraction : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; def int_AMDIL_fraction : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;

2
lib/Target/X86/X86FastISel.cpp
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@ -1315,7 +1315,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight); FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
// Emits an unconditional branch to the FalseBB, obtains the branch // Emits an unconditional branch to the FalseBB, obtains the branch
// weight, andd adds it to the successor list. // weight, and adds it to the successor list.
FastEmitBranch(FalseMBB, DbgLoc); FastEmitBranch(FalseMBB, DbgLoc);
return true; return true;

8
test/CodeGen/PowerPC/vec_cmp.ll
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@ -36,7 +36,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; Adicional tests for v16i8 since it is a altivec native type ; Additional tests for v16i8 since it is a altivec native type
define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone { define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%cmp = icmp eq <16 x i8> %x, %y %cmp = icmp eq <16 x i8> %x, %y
@ -165,7 +165,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; Adicional tests for v8i16 since it is an altivec native type ; Additional tests for v8i16 since it is an altivec native type
define <8 x i16> @v8si16_cmp_eq(<8 x i16> %x, <8 x i16> %y) nounwind readnone { define <8 x i16> @v8si16_cmp_eq(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
entry: entry:
@ -298,7 +298,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; Adicional tests for v4si32 since it is an altivec native type ; Additional tests for v4si32 since it is an altivec native type
define <4 x i32> @v4si32_cmp_eq(<4 x i32> %x, <4 x i32> %y) nounwind readnone { define <4 x i32> @v4si32_cmp_eq(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
entry: entry:
@ -449,7 +449,7 @@ entry:
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; Adicional tests for v4f32 since it is a altivec native type ; Additional tests for v4f32 since it is a altivec native type
define <4 x float> @v4f32_cmp_eq(<4 x float> %x, <4 x float> %y) nounwind readnone { define <4 x float> @v4f32_cmp_eq(<4 x float> %x, <4 x float> %y) nounwind readnone {
entry: entry:

2
test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
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@ -1,5 +1,5 @@
; RUN: llc %s -o /dev/null ; RUN: llc %s -o /dev/null
; Here variable bar is optimzied away. Do not trip over while trying to generate debug info. ; Here variable bar is optimized away. Do not trip over while trying to generate debug info.
define i32 @foo() nounwind uwtable readnone ssp { define i32 @foo() nounwind uwtable readnone ssp {