6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-02 04:24:22 +00:00
Code Issues Projects Releases Wiki Activity

Fix encoding of single-precision VFP registers.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-11-12 02:19:38 +00:00
parent cbf7cf50ec
commit d06d48d2b5
4 changed files with 176 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -81,6 +81,80 @@ unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
}
}
unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum,
bool &isSPVFP) {
isSPVFP = false;
using namespace ARM;
switch (RegEnum) {
default:
assert(0 && "Unknown ARM register!");
abort();
case R0: case D0: return 0;
case R1: case D1: return 1;
case R2: case D2: return 2;
case R3: case D3: return 3;
case R4: case D4: return 4;
case R5: case D5: return 5;
case R6: case D6: return 6;
case R7: case D7: return 7;
case R8: case D8: return 8;
case R9: case D9: return 9;
case R10: case D10: return 10;
case R11: case D11: return 11;
case R12: case D12: return 12;
case SP: case D13: return 13;
case LR: case D14: return 14;
case PC: case D15: return 15;
case S0: case S1: case S2: case S3:
case S4: case S5: case S6: case S7:
case S8: case S9: case S10: case S11:
case S12: case S13: case S14: case S15:
case S16: case S17: case S18: case S19:
case S20: case S21: case S22: case S23:
case S24: case S25: case S26: case S27:
case S28: case S29: case S30: case S31: {
isSPVFP = true;
switch (RegEnum) {
default: return 0; // Avoid compile time warning.
case S0: return 0;
case S1: return 1;
case S2: return 2;
case S3: return 3;
case S4: return 4;
case S5: return 5;
case S6: return 6;
case S7: return 7;
case S8: return 8;
case S9: return 9;
case S10: return 10;
case S11: return 11;
case S12: return 12;
case S13: return 13;
case S14: return 14;
case S15: return 15;
case S16: return 16;
case S17: return 17;
case S18: return 18;
case S19: return 19;
case S20: return 20;
case S21: return 21;
case S22: return 22;
case S23: return 23;
case S24: return 24;
case S25: return 25;
case S26: return 26;
case S27: return 27;
case S28: return 28;
case S29: return 29;
case S30: return 30;
case S31: return 31;
}
}
}
}
ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
const ARMSubtarget &sti)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),