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R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

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Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-05-23 18:26:42 +00:00
parent 5c35290fa3
commit d078070f6a
2 changed files with 31 additions and 2 deletions
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11
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -117,8 +117,15 @@ private:
const MachineOperand &MO = *I;
if (!MO.isReg())
continue;
if (MO.isDef())
DstMI = MO.getReg();
if (MO.isDef()) {
unsigned Reg = MO.getReg();
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
DstMI = Reg;
else
DstMI = TRI.getMatchingSuperReg(Reg,
TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
if (MO.isUse()) {
unsigned Reg = MO.getReg();
if (AMDGPU::R600_Reg128RegClass.contains(Reg))

22
test/CodeGen/R600/vtx-schedule.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; This test is for a scheduler bug where VTX_READ instructions that used
; the result of another VTX_READ instruction were being grouped in the
; same fetch clasue.
; CHECK: @test
; CHECK: Fetch clause
; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40
; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44
; CHECK: Fetch clause
; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) {
entry:
%0 = load i32 addrspace(1)* %in0, align 4
%1 = load i32 addrspace(1)* %in1, align 4
%cmp.i = icmp slt i32 %0, %1
%cond.i = select i1 %cmp.i, i32 %0, i32 %1
store i32 %cond.i, i32 addrspace(1)* %out, align 4
ret void
}