From d088834fb991d96b4b34aaae7ff68dc413ecec9a Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Fri, 22 Jul 2011 00:14:56 +0000 Subject: [PATCH] Introduce a new function to lower 256-bit vectors which are not direclty supported and should be promoted and handled by smaller shuffles git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135726 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 17d47e7c822..85c6f492351 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5376,6 +5376,13 @@ static SDValue getVZextMovL(EVT VT, EVT OpVT, OpVT, SrcOp))); } +/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles +/// which could not be matched by any known target speficic shuffle +static SDValue +LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { + return SDValue(); +} + /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with /// 4 elements, and match them with several different shuffle types. static SDValue @@ -6101,6 +6108,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { if (NumElems == 4 && VT.getSizeInBits() == 128) return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); + //===--------------------------------------------------------------------===// + // Custom lower or generate target specific nodes for 256-bit shuffles. + // Handle VPERMIL permutations if (isVPERMILMask(M, VT)) { unsigned TargetMask = getShuffleVPERMILImmediate(SVOp); @@ -6108,6 +6118,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { return getTargetShuffleNode(X86ISD::VPERMIL, dl, VT, V1, TargetMask, DAG); } + // Handle general 256-bit shuffles + if (VT.is256BitVector()) + return LowerVECTOR_SHUFFLE_256(SVOp, DAG); + return SDValue(); }