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Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -740,9 +740,9 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
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const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
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const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
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unsigned OffsetWidth = 4;
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if (MI->getOpcode() == ARM::t2TBB)
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if (MI->getOpcode() == ARM::t2TBB_JT)
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OffsetWidth = 1;
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else if (MI->getOpcode() == ARM::t2TBH)
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else if (MI->getOpcode() == ARM::t2TBH_JT)
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OffsetWidth = 2;
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for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
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@ -777,7 +777,7 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
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// Make sure the instruction that follows TBB is 2-byte aligned.
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// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
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if (MI->getOpcode() == ARM::t2TBB)
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if (MI->getOpcode() == ARM::t2TBB_JT)
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EmitAlignment(1);
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}
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@ -924,8 +924,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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case ARM::t2TBB:
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case ARM::t2TBH:
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case ARM::t2TBB_JT:
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case ARM::t2TBH_JT:
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case ARM::t2BR_JT: {
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// Lower and emit the instruction itself, then the jump table following it.
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MCInst TmpInst;
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@ -518,13 +518,13 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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case ARM::BR_JTadd:
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case ARM::tBR_JTr:
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case ARM::t2BR_JT:
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case ARM::t2TBB:
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case ARM::t2TBH: {
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case ARM::t2TBB_JT:
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case ARM::t2TBH_JT: {
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// These are jumptable branches, i.e. a branch followed by an inlined
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// jumptable. The size is 4 + 4 * number of entries. For TBB, each
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// entry is one byte; TBH two byte each.
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unsigned EntrySize = (Opc == ARM::t2TBB)
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? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
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unsigned EntrySize = (Opc == ARM::t2TBB_JT)
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? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
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unsigned NumOps = TID.getNumOperands();
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MachineOperand JTOP =
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MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
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@ -542,7 +542,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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// alignment issue.
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unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
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unsigned NumEntries = getNumJTEntries(JT, JTI);
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if (Opc == ARM::t2TBB && (NumEntries & 1))
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if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
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// Make sure the instruction that follows TBB is 2-byte aligned.
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// FIXME: Constant island pass should insert an "ALIGN" instruction
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// instead.
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@ -1766,7 +1766,7 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
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if (!OptOk)
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continue;
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unsigned Opc = ByteOk ? ARM::t2TBB : ARM::t2TBH;
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unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
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MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
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.addReg(IdxReg, getKillRegState(IdxRegKill))
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.addJumpTableIndex(JTI, JTOP.getTargetFlags())
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@ -2947,7 +2947,7 @@ def t2BR_JT :
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// FIXME: Add a non-pc based case that can be predicated.
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let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
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def t2TBB :
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def t2TBB_JT :
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T2JTI<(outs),
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(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
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IIC_Br, "tbb\t$index$jt", []> {
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@ -2959,7 +2959,7 @@ def t2TBB :
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}
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let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
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def t2TBH :
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def t2TBH_JT :
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T2JTI<(outs),
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(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
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IIC_Br, "tbh\t$index$jt", []> {
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@ -531,7 +531,7 @@ void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
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void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
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if (MI->getOpcode() == ARM::t2TBH)
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if (MI->getOpcode() == ARM::t2TBH_JT)
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O << ", lsl #1";
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O << ']';
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}
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@ -1719,7 +1719,7 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
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return false;
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// Ignore t2TBB, t2TBH and prefer the generic t2TBBgen, t2TBHgen.
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if (Name == "t2TBB" || Name == "t2TBH")
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if (Name == "t2TBB_JT" || Name == "t2TBH_JT")
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return false;
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// Resolve conflicts:
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