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[mips] Change existing uimm10 operand to restrict the accepted immediates

Browse Source 
http://reviews.llvm.org/D10312


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2015-06-11 09:51:58 +00:00
parent 938cba6ae3
commit d09e8beec3
5 changed files with 24 additions and 0 deletions
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3
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -879,6 +879,9 @@ public:
bool isConstantImm() const {
return isImm() && dyn_cast<MCConstantExpr>(getImm());
}
template <unsigned Bits> bool isUImm() const {
return isImm() && isConstantImm() && isUInt<Bits>(getConstantImm());
}
bool isToken() const override {
// Note: It's not possible to pretend that other operand kinds are tokens.
// The matcher emitter checks tokens first.

8
lib/Target/Mips/MipsInstrInfo.td
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@ -384,7 +384,15 @@ def simm20 : Operand<i32> {
def uimm20 : Operand<i32> {
}
def MipsUImm10AsmOperand : AsmOperandClass {
let Name = "UImm10";
let RenderMethod = "addImmOperands";
let ParserMethod = "parseImm";
let PredicateMethod = "isUImm<10>";
}
def uimm10 : Operand<i32> {
let ParserMatchClass = MipsUImm10AsmOperand;
}
def simm16_64 : Operand<i64> {

5
test/MC/Mips/micromips-invalid.s
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@ -73,3 +73,8 @@
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

4
test/MC/Mips/mips32r6/invalid.s
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@ -12,3 +12,7 @@
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

4
test/MC/Mips/mips64r6/invalid.s
View File

@ -10,3 +10,7 @@
jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction