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Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM

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stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-04-12 02:24:17 +00:00
parent 39df9b5920
commit d0aacbcc2e
2 changed files with 23 additions and 3 deletions
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24
lib/Target/ARM/ARMISelLowering.cpp
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@ -5684,8 +5684,28 @@ static SDValue PerformSTORECombine(SDNode *N,
// Otherwise, the i64 value will be legalized to a pair of i32 values.
StoreSDNode *St = cast<StoreSDNode>(N);
SDValue StVal = St->getValue();
if (!ISD::isNormalStore(St) || St->isVolatile() ||
StVal.getValueType() != MVT::i64 ||
if (!ISD::isNormalStore(St) || St->isVolatile())
return SDValue();
if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
StVal.getNode()->hasOneUse() && !St->isVolatile()) {
SelectionDAG &DAG = DCI.DAG;
DebugLoc DL = St->getDebugLoc();
SDValue BasePtr = St->getBasePtr();
SDValue NewST1 = DAG.getStore(St->getChain(), DL,
StVal.getNode()->getOperand(0), BasePtr,
St->getPointerInfo(), St->isVolatile(),
St->isNonTemporal(), St->getAlignment());
SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
DAG.getConstant(4, MVT::i32));
return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
OffsetPtr, St->getPointerInfo(), St->isVolatile(),
St->isNonTemporal(),
std::min(4U, St->getAlignment() / 2));
}
if (StVal.getValueType() != MVT::i64 ||
StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
return SDValue();

2
test/CodeGen/ARM/fp-arg-shuffle.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s
; CHECK: function1
; CHECK-NOT: vmov r
; CHECK-NOT: vmov
define double @function1(double %a, double %b, double %c, double %d, double %e, double %f) nounwind noinline ssp {
entry:
%call = tail call double @function2(double %f, double %e, double %d, double %c, double %b, double %a) nounwind