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Fix return before else

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-05-11 21:24:41 +00:00
parent 70a83b490e
commit d0c1b54942
1 changed files with 18 additions and 18 deletions
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36
lib/Target/R600/AMDGPUISelLowering.cpp
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@@ -531,13 +531,17 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr, return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
MachinePointerInfo(UndefValue::get(PtrTy)), false, false, MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
TD->getPrefTypeAlignment(CI->getType())); TD->getPrefTypeAlignment(CI->getType()));
} else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) { }
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
EVT VT = EVT::getEVT(CFP->getType()); EVT VT = EVT::getEVT(CFP->getType());
PointerType *PtrTy = PointerType::get(CFP->getType(), 0); PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr, return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
MachinePointerInfo(UndefValue::get(PtrTy)), false, false, MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
TD->getPrefTypeAlignment(CFP->getType())); TD->getPrefTypeAlignment(CFP->getType()));
} else if (Init->getType()->isAggregateType()) { }
if (Init->getType()->isAggregateType()) {
EVT PtrVT = InitPtr.getValueType(); EVT PtrVT = InitPtr.getValueType();
unsigned NumElements = Init->getType()->getArrayNumElements(); unsigned NumElements = Init->getType()->getArrayNumElements();
SmallVector<SDValue, 8> Chains; SmallVector<SDValue, 8> Chains;
@@ -548,11 +552,12 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i), Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
GV, Ptr, Chain, DAG)); GV, Ptr, Chain, DAG));
} }
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
} else {
Init->dump();
llvm_unreachable("Unhandled constant initializer");
} }
Init->dump();
llvm_unreachable("Unhandled constant initializer");
} }
SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI, SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
@@ -724,8 +729,7 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
///IABS(a) = SMAX(sub(0, a), a) ///IABS(a) = SMAX(sub(0, a), a)
SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
@@ -737,7 +741,7 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
/// Linear Interpolation /// Linear Interpolation
/// LRP(a, b, c) = muladd(a, b, (1 - a) * c) /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
@@ -752,7 +756,7 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
/// \brief Generate Min/Max node /// \brief Generate Min/Max node
SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N, SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(N); SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
@@ -788,10 +792,8 @@ SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
case ISD::SETOLT: case ISD::SETOLT:
case ISD::SETLE: case ISD::SETLE:
case ISD::SETLT: { case ISD::SETLT: {
if (LHS == True) unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
else
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
} }
case ISD::SETGT: case ISD::SETGT:
case ISD::SETGE: case ISD::SETGE:
@@ -799,10 +801,8 @@ SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
case ISD::SETOGE: case ISD::SETOGE:
case ISD::SETUGT: case ISD::SETUGT:
case ISD::SETOGT: { case ISD::SETOGT: {
if (LHS == True) unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
else
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
} }
case ISD::SETCC_INVALID: case ISD::SETCC_INVALID:
llvm_unreachable("Invalid setcc condcode!"); llvm_unreachable("Invalid setcc condcode!");
@@ -1049,7 +1049,7 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
} }
SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();