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Fix a dagga combiner bug: avoid creating illegal constant.

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Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76535 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-21 05:40:15 +00:00
parent f53c371983
commit d101a72d79
2 changed files with 41 additions and 9 deletions
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5
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2475,8 +2475,10 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
if (c1 < VT.getSizeInBits()) {
uint64_t c2 = N1C->getZExtValue();
SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
N0.getOperand(0),
DAG.getConstant(~0ULL << c1, VT));
if (c2 > c1)
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
@ -2485,6 +2487,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
DAG.getConstant(c1-c2, N1.getValueType()));
}
}
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),

29
test/CodeGen/X86/2009-07-20-DAGCombineBug.ll Normal file
View File

@ -0,0 +1,29 @@
; RUN: llvm-as < %s | llc -march=x86
@bsBuff = internal global i32 0 ; <i32*> [#uses=1]
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @bsGetUInt32 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define fastcc i32 @bsGetUInt32() nounwind ssp {
entry:
%bsBuff.promoted44 = load i32* @bsBuff ; <i32> [#uses=1]
%0 = add i32 0, -8 ; <i32> [#uses=1]
%1 = lshr i32 %bsBuff.promoted44, %0 ; <i32> [#uses=1]
%2 = shl i32 %1, 8 ; <i32> [#uses=1]
br label %bb3.i17
bb3.i9: ; preds = %bb3.i17
br i1 false, label %bb2.i16, label %bb1.i15
bb1.i15: ; preds = %bb3.i9
unreachable
bb2.i16: ; preds = %bb3.i9
br label %bb3.i17
bb3.i17: ; preds = %bb2.i16, %entry
br i1 false, label %bb3.i9, label %bsR.exit18
bsR.exit18: ; preds = %bb3.i17
%3 = or i32 0, %2 ; <i32> [#uses=0]
ret i32 0
}