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Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the

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Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2007-12-31 06:32:00 +00:00
parent f20c1a497f
commit d10fd9791c
31 changed files with 321 additions and 267 deletions
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28
lib/Target/ARM/ARMRegisterInfo.cpp
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@@ -270,34 +270,6 @@ void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
return;
}
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
}
if (DestRC == ARM::GPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction())
BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
else
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg)
.addReg(SrcReg)));
} else if (DestRC == ARM::SPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg)
.addReg(SrcReg));
else if (DestRC == ARM::DPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
else
abort();
}
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
static void emitLoadConstPool(MachineBasicBlock &MBB,