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https://github.com/c64scene-ar/llvm-6502.git
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These nodes are all autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23489 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -678,25 +678,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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return SDOperand(N, 0);
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}
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case ISD::Constant: {
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assert(N->getValueType(0) == MVT::i32);
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unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
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// NOTE: This doesn't use SelectNodeTo, because doing that will prevent
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// folding shared immediates into other the second instruction that
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// uses it.
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if (isInt16(v))
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return CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(v));
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unsigned Hi = Hi16(v);
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unsigned Lo = Lo16(v);
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if (!Lo)
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return CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi));
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SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi));
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return CurDAG->getTargetNode(PPC::ORI, MVT::i32, Top, getI32Imm(Lo));
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}
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i32)
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CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
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@ -768,21 +749,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->ReplaceAllUsesWith(N, Result.Val);
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return SDOperand(Result.Val, Op.ResNo);
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}
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case ISD::SIGN_EXTEND_INREG:
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switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
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default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
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case MVT::i16:
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CurDAG->SelectNodeTo(N, PPC::EXTSH, MVT::i32, Select(N->getOperand(0)));
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break;
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case MVT::i8:
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CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0)));
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break;
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}
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return SDOperand(N, 0);
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case ISD::CTLZ:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
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return SDOperand(N, 0);
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case PPCISD::FSEL:
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CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
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Select(N->getOperand(0)),
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@ -960,16 +926,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::MULHS:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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case ISD::MULHU:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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case ISD::AND: {
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unsigned Imm;
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// If this is an and of a value rotated between 0 and 31 bits and then and'd
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