6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-12 13:30:51 +00:00
Code Issues Projects Releases Wiki Activity

Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-12-11 03:32:44 +00:00
parent ec5ebdec47
commit d194a4ae67
3 changed files with 80 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
View File

@ -85,12 +85,20 @@ void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
O << "\t.set\tmips32r2\n";
break;
case Mips::Save16:
O << "\tsave\t";
printSaveRestore(MI, O);
O << " # 16 bit inst\n";
return;
case Mips::SaveX16:
O << "\tsave\t";
printSaveRestore(MI, O);
O << "\n";
return;
case Mips::Restore16:
O << "\trestore\t";
printSaveRestore(MI, O);
O << " # 16 bit inst\n";
return;
case Mips::RestoreX16:
O << "\trestore\t";
printSaveRestore(MI, O);

12
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -1,3 +1,4 @@
//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
//
// The LLVM Compiler Infrastructure
@ -176,9 +177,10 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
const BitVector Reserved = RI.getReservedRegs(*MBB.getParent());
bool SaveS2 = Reserved[Mips::S2];
MachineInstrBuilder MIB;
unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
if (isUInt<11>(FrameSize))
MIB = BuildMI(
MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
MBB, I, DL, get(Opc)).addReg(Mips::RA).
addReg(Mips::S0).
addReg(Mips::S1).addImm(FrameSize);
else {
@ -186,7 +188,7 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
// returns largest possible n bit unsigned integer
int64_t Remainder = FrameSize - Base;
MIB = BuildMI(
MBB, I, DL, get(Mips::SaveX16)).addReg(Mips::RA).
MBB, I, DL, get(Opc)).addReg(Mips::RA).
addReg(Mips::S0).
addReg(Mips::S1).addImm(Base);
if (isInt<16>(-Remainder))
@ -206,9 +208,11 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
const BitVector Reserved = RI.getReservedRegs(*MBB.getParent());
bool SaveS2 = Reserved[Mips::S2];
MachineInstrBuilder MIB;
unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
Mips::Restore16:Mips::RestoreX16;
if (isUInt<11>(FrameSize))
MIB = BuildMI(
MBB, I, DL, get(Mips::RestoreX16)).
MBB, I, DL, get(Opc)).
addReg(Mips::RA, RegState::Define).
addReg(Mips::S0, RegState::Define).
addReg(Mips::S1, RegState::Define).
@ -222,7 +226,7 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
else
adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
MIB = BuildMI(
MBB, I, DL, get(Mips::RestoreX16)).
MBB, I, DL, get(Opc)).
addReg(Mips::RA, RegState::Define).
addReg(Mips::S0, RegState::Define).
addReg(Mips::S1, RegState::Define).

64
test/CodeGen/Mips/sr1.ll Normal file
View File

@ -0,0 +1,64 @@
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=NEG
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s
@f = common global float 0.000000e+00, align 4
; Function Attrs: nounwind
define void @foo1() #0 {
entry:
%c = alloca [10 x i8], align 1
%arraydecay = getelementptr inbounds [10 x i8]* %c, i32 0, i32 0
call void @x(i8* %arraydecay)
%arraydecay1 = getelementptr inbounds [10 x i8]* %c, i32 0, i32 0
call void @x(i8* %arraydecay1)
ret void
; CHECK: .ent foo1
; CHECK: save $ra, $16, $17, [[FS:[0-9]+]] # 16 bit inst
; CHECK: restore $ra, $16, $17, [[FS]]
; CHECK: .end foo1
}
declare void @x(i8*) #1
; Function Attrs: nounwind
define void @foo2() #0 {
entry:
%c = alloca [150 x i8], align 1
%arraydecay = getelementptr inbounds [150 x i8]* %c, i32 0, i32 0
call void @x(i8* %arraydecay)
%arraydecay1 = getelementptr inbounds [150 x i8]* %c, i32 0, i32 0
call void @x(i8* %arraydecay1)
ret void
; CHECK: .ent foo2
; CHECK: save $ra, $16, $17, [[FS:[0-9]+]]
; CHECK: restore $ra, $16, $17, [[FS]]
; CHECK: .end foo2
; NEG: .ent foo2
; NEG-NOT: save $ra, $16, $17, [[FS:[0-9]+]] # 16 bit inst
; NEG-NOT: restore $ra, $16, $17, [[FS]] # 16 bit inst
; NEG: .end foo2
}
; Function Attrs: nounwind
define void @foo3() #0 {
entry:
%call = call float @xf()
store float %call, float* @f, align 4
ret void
; CHECK: .ent foo3
; CHECK: save $ra, $16, $17, [[FS:[0-9]+]], $18
; CHECK: restore $ra, $16, $17, [[FS]], $18
; CHECK: .end foo3
; NEG: .ent foo3
; NEG-NOT: save $ra, $16, $17, [[FS:[0-9]+]], $18 # 16 bit inst
; NEG-NOT: restore $ra, $16, $17, [[FS]], $18 # 16 bit inst
; NEG: .end foo3
}
declare float @xf() #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }