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Drop support for Allegrex. Allegrex implements a variant of Mips2.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-09 19:00:51 +00:00
parent b6aed508e3
commit d199d0c59c
10 changed files with 33 additions and 39 deletions
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7
lib/Target/Mips/Mips.td
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@ -82,13 +82,6 @@ def : Proc<"r6000", [FeatureMips2]>;
def : Proc<"mips32r1", [FeatureMips32]>;
def : Proc<"4ke", [FeatureMips32r2]>;
// Allegrex is a 32bit subset of r4000, both for integer and fp registers,
// but much more similar to Mips2 than Mips3. It also contains some of
// Mips32/Mips32r2 instructions and a custom vector fpu processor.
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
FeatureMinMax, FeatureSwap, FeatureBitCount]>;
def MipsAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
bit isMCAsmWriter = 1;

16
lib/Target/Mips/MipsSubtarget.cpp
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@ -42,20 +42,4 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
// Is the target system Linux ?
if (TT.find("linux") == std::string::npos)
IsLinux = false;
// When only the target triple is specified and is
// a allegrex target, set the features. We also match
// big and little endian allegrex cores (dont really
// know if a big one exists)
if (TT.find("mipsallegrex") != std::string::npos ||
TT.find("psp") != std::string::npos) {
MipsABI = EABI;
IsSingleFloat = true;
MipsArchVersion = Mips2;
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
HasSEInReg = true;
HasBitCount = true;
HasSwap = true;
HasCondMov = true;
}
}

4
test/CodeGen/Mips/2008-07-05-ByVal.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=mips | grep {lw.*(\$4)} | count 2
; DISABLED: llc < %s -march=mips | grep {lw.*(\$4)} | count 2
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

4
test/CodeGen/Mips/2008-07-06-fadd64.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=mips | grep __adddf3
; DISABLED: llc < %s -march=mips | grep __adddf3
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

4
test/CodeGen/Mips/2008-07-07-FPExtend.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=mips | grep __extendsfdf2
; DISABLED: llc < %s -march=mips | grep __extendsfdf2
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

12
test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
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@ -1,8 +1,10 @@
; RUN: llc < %s -march=mips -o %t
; RUN: grep __floatsidf %t | count 1
; RUN: grep __floatunsidf %t | count 1
; RUN: grep __fixdfsi %t | count 1
; RUN: grep __fixunsdfsi %t | count 1
; DISABLED: llc < %s -march=mips -o %t
; DISABLED: grep __floatsidf %t | count 1
; DISABLED: grep __floatunsidf %t | count 1
; DISABLED: grep __fixdfsi %t | count 1
; DISABLED: grep __fixunsdfsi %t | count 1
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

8
test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
View File

@ -1,6 +1,8 @@
; RUN: llc < %s -march=mips -o %t
; RUN: grep seh %t | count 1
; RUN: grep seb %t | count 1
; DISABLED: llc < %s -march=mips -o %t
; DISABLED: grep seh %t | count 1
; DISABLED: grep seb %t | count 1
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

8
test/CodeGen/Mips/2008-08-03-fabs64.ll
View File

@ -1,6 +1,8 @@
; RUN: llc < %s -march=mips -o %t
; RUN: grep {lui.*32767} %t | count 1
; RUN: grep {ori.*65535} %t | count 1
; DISABLED: llc < %s -march=mips -o %t
; DISABLED: grep {lui.*32767} %t | count 1
; DISABLED: grep {ori.*65535} %t | count 1
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

4
test/CodeGen/Mips/2008-08-07-FPRound.ll
View File

@ -1,4 +1,6 @@
; RUN: llc < %s -march=mips | grep __truncdfsf2 | count 1
; DISABLED: llc < %s -march=mips | grep __truncdfsf2 | count 1
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"

5
test/CodeGen/Mips/2008-08-08-bswap.ll
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@ -1,4 +1,7 @@
; RUN: llc < %s | grep wsbw | count 1
; DISABLED: llc < %s | grep wsbw | count 1
; RUN: false
; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "psp"