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Add Thumb encodings for REV instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-29 00:42:50 +00:00
parent b4b544deba
commit d19ac0c75a
2 changed files with 44 additions and 19 deletions
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54
lib/Target/ARM/ARMInstrThumb.td
View File

@ -1028,30 +1028,48 @@ def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
}
// Swaps
def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"rev", "\t$dst, $src",
[(set tGPR:$dst, (bswap tGPR:$src))]>,
def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
"rev", "\t$Rd, $Rm",
[(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
Requires<[IsThumb, IsThumb1Only, HasV6]>,
T1Misc<{1,0,1,0,0,0,?}>;
T1Misc<{1,0,1,0,0,0,?}> {
// A8.6.134
bits<3> Rm;
bits<3> Rd;
let Inst{5-3} = Rm;
let Inst{2-0} = Rd;
}
def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"rev16", "\t$dst, $src",
[(set tGPR:$dst,
(or (and (srl tGPR:$src, (i32 8)), 0xFF),
(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
(or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
def tREV16 : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
"rev16", "\t$Rd, $Rm",
[(set tGPR:$Rd,
(or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
(or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
(or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
(and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
Requires<[IsThumb, IsThumb1Only, HasV6]>,
T1Misc<{1,0,1,0,0,1,?}>;
T1Misc<{1,0,1,0,0,1,?}> {
// A8.6.135
bits<3> Rm;
bits<3> Rd;
let Inst{5-3} = Rm;
let Inst{2-0} = Rd;
}
def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"revsh", "\t$dst, $src",
[(set tGPR:$dst,
def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
"revsh", "\t$Rd, $Rm",
[(set tGPR:$Rd,
(sext_inreg
(or (srl (and tGPR:$src, 0xFF00), (i32 8)),
(shl tGPR:$src, (i32 8))), i16))]>,
(or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
(shl tGPR:$Rm, (i32 8))), i16))]>,
Requires<[IsThumb, IsThumb1Only, HasV6]>,
T1Misc<{1,0,1,0,1,1,?}>;
T1Misc<{1,0,1,0,1,1,?}> {
// A8.6.135
bits<3> Rm;
bits<3> Rd;
let Inst{5-3} = Rm;
let Inst{2-0} = Rd;
}
// rotate right register
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,

9
test/MC/ARM/thumb.s
View File

@ -1,4 +1,4 @@
@ RUN: llvm-mc -triple thumb-apple-darwin -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
.code 16
@ CHECK: cmp r1, r2 @ encoding: [0x91,0x42]
@ -12,3 +12,10 @@
@ CHECK: blx r9 @ encoding: [0xc8,0x47]
blx r9
@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba]
@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
@ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba]
rev r2, r3
rev16 r3, r4
revsh r5, r6