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Make sure the regs are low regs for tMUL size reduction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-02-24 00:53:11 +00:00
parent fdf7c85032
commit d1b220a33b
1 changed files with 6 additions and 1 deletions
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7
lib/Target/ARM/Thumb2SizeReduction.cpp
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@ -599,7 +599,12 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg1 = MI->getOperand(1).getReg();
// t2MUL is "special". The tied source operand is second, not first. // t2MUL is "special". The tied source operand is second, not first.
if (MI->getOpcode() == ARM::t2MUL) { if (MI->getOpcode() == ARM::t2MUL) {
if (Reg0 != MI->getOperand(2).getReg()) { unsigned Reg2 = MI->getOperand(2).getReg();
// Early exit if the regs aren't all low regs.
if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
|| !isARMLowRegister(Reg2))
return false;
if (Reg0 != Reg2) {
// If the other operand also isn't the same as the destination, we // If the other operand also isn't the same as the destination, we
// can't reduce. // can't reduce.
if (Reg1 != Reg0) if (Reg1 != Reg0)