mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
Variable cleanup. Based on past patch submittals variable names have
been normalized and more descriptive comments added. Patch by Reed Kotler and Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146088 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
0e6307f642
commit
d1bcf0dbc1
@ -14,77 +14,82 @@
|
||||
|
||||
namespace llvm {
|
||||
namespace Mips {
|
||||
enum Fixups {
|
||||
// fixup_Mips_xxx - R_MIPS_NONE
|
||||
fixup_Mips_NONE = FirstTargetFixupKind,
|
||||
// Although most of the current fixup types reflect a unique relocation
|
||||
// one can have multiple fixup types for a given relocation and thus need
|
||||
// to be uniquely named.
|
||||
//
|
||||
// This table *must* be in the save order of
|
||||
// MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
|
||||
// in MipsAsmBackend.cpp.
|
||||
//
|
||||
enum Fixups {
|
||||
// Branch fixups resulting in R_MIPS_16.
|
||||
fixup_Mips_16 = FirstTargetFixupKind,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_16.
|
||||
fixup_Mips_16,
|
||||
// Pure 32 bit data fixup resulting in - R_MIPS_32.
|
||||
fixup_Mips_32,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_32.
|
||||
fixup_Mips_32,
|
||||
// Full 32 bit data relative data fixup resulting in - R_MIPS_REL32.
|
||||
fixup_Mips_REL32,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_REL32.
|
||||
fixup_Mips_REL32,
|
||||
// Jump 26 bit fixup resulting in - R_MIPS_26.
|
||||
fixup_Mips_26,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_26.
|
||||
fixup_Mips_26,
|
||||
// Pure upper 16 bit fixup resulting in - R_MIPS_HI16.
|
||||
fixup_Mips_HI16,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_HI16.
|
||||
fixup_Mips_HI16,
|
||||
// Pure lower 16 bit fixup resulting in - R_MIPS_LO16.
|
||||
fixup_Mips_LO16,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_LO16.
|
||||
fixup_Mips_LO16,
|
||||
// 16 bit fixup for GP offest resulting in - R_MIPS_GPREL16.
|
||||
fixup_Mips_GPREL16,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_GPREL16.
|
||||
fixup_Mips_GPREL16,
|
||||
// 16 bit literal fixup resulting in - R_MIPS_LITERAL.
|
||||
fixup_Mips_LITERAL,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_LITERAL.
|
||||
fixup_Mips_LITERAL,
|
||||
// Global symbol fixup resulting in - R_MIPS_GOT16.
|
||||
fixup_Mips_GOT_Global,
|
||||
|
||||
// Global symbol fixup resulting in - R_MIPS_GOT16.
|
||||
fixup_Mips_GOT_Global,
|
||||
// Local symbol fixup resulting in - R_MIPS_GOT16.
|
||||
fixup_Mips_GOT_Local,
|
||||
|
||||
// Local symbol fixup resulting in - R_MIPS_GOT16.
|
||||
fixup_Mips_GOT_Local,
|
||||
// PC relative branch fixup resulting in - R_MIPS_PC16.
|
||||
fixup_Mips_PC16,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_PC16.
|
||||
fixup_Mips_PC16,
|
||||
// resulting in - R_MIPS_CALL16.
|
||||
fixup_Mips_CALL16,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_CALL16.
|
||||
fixup_Mips_CALL16,
|
||||
// resulting in - R_MIPS_GPREL32.
|
||||
fixup_Mips_GPREL32,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_GPREL32.
|
||||
fixup_Mips_GPREL32,
|
||||
// resulting in - R_MIPS_SHIFT5.
|
||||
fixup_Mips_SHIFT5,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_SHIFT5.
|
||||
fixup_Mips_SHIFT5,
|
||||
// resulting in - R_MIPS_SHIFT6.
|
||||
fixup_Mips_SHIFT6,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_SHIFT6.
|
||||
fixup_Mips_SHIFT6,
|
||||
// Pure 64 bit data fixup resulting in - R_MIPS_64.
|
||||
fixup_Mips_64,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_64.
|
||||
fixup_Mips_64,
|
||||
// resulting in - R_MIPS_TLS_GD.
|
||||
fixup_Mips_TLSGD,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_TLS_GD.
|
||||
fixup_Mips_TLSGD,
|
||||
// resulting in - R_MIPS_TLS_GOTTPREL.
|
||||
fixup_Mips_GOTTPREL,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_TLS_GOTTPREL.
|
||||
fixup_Mips_GOTTPREL,
|
||||
// resulting in - R_MIPS_TLS_TPREL_HI16.
|
||||
fixup_Mips_TPREL_HI,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_TLS_TPREL_HI16.
|
||||
fixup_Mips_TPREL_HI,
|
||||
// resulting in - R_MIPS_TLS_TPREL_LO16.
|
||||
fixup_Mips_TPREL_LO,
|
||||
|
||||
// fixup_Mips_xxx - R_MIPS_TLS_TPREL_LO16.
|
||||
fixup_Mips_TPREL_LO,
|
||||
// PC relative branch fixup resulting in - R_MIPS_PC16
|
||||
fixup_Mips_Branch_PCRel,
|
||||
|
||||
// fixup_Mips_xxx - yyy. // This should become R_MIPS_PC16
|
||||
fixup_Mips_Branch_PCRel,
|
||||
|
||||
// Marker
|
||||
LastTargetFixupKind,
|
||||
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
|
||||
};
|
||||
// Marker
|
||||
LastTargetFixupKind,
|
||||
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
|
||||
};
|
||||
} // namespace Mips
|
||||
} // namespace llvm
|
||||
|
||||
|
@ -248,8 +248,8 @@ unsigned
|
||||
MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
assert(MI.getOperand(OpNo).isImm());
|
||||
unsigned szEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
||||
return szEncoding - 1;
|
||||
unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
||||
return SizeEncoding - 1;
|
||||
}
|
||||
|
||||
// FIXME: should be called getMSBEncoding
|
||||
@ -259,10 +259,10 @@ MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
assert(MI.getOperand(OpNo-1).isImm());
|
||||
assert(MI.getOperand(OpNo).isImm());
|
||||
unsigned pos = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
|
||||
unsigned sz = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
||||
unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
|
||||
unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
||||
|
||||
return pos + sz - 1;
|
||||
return Position + Size - 1;
|
||||
}
|
||||
|
||||
#include "MipsGenMCCodeEmitter.inc"
|
||||
|
Loading…
Reference in New Issue
Block a user