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[mips] Add NaCl target and forbid indexed loads and stores for it

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This patch adds NaCl target for Mips. It also forbids indexed loads and
stores if the target is NaCl.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2690


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200855 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Petar Jovanovic 2014-02-05 17:19:30 +00:00
parent 0644c7a8ab
commit d1dc9a0af0
5 changed files with 17 additions and 4 deletions
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9
lib/Target/Mips/MipsInstrFPU.td
View File

@ -390,12 +390,15 @@ let Predicates = [HasStdEnc] in {
}
// Indexed loads and stores.
let Predicates = [HasFPIdx, HasStdEnc] in {
// Base register + offset register addressing mode (indicated by "x" in the
// instruction mnemonic) is disallowed under NaCl.
let Predicates = [HasFPIdx, HasStdEnc, IsNotNaCl] in {
def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
}
let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips] in {
let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips,
IsNotNaCl] in {
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
}
@ -407,7 +410,7 @@ let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
}
// Load/store doubleword indexed unaligned.
let Predicates = [NotFP64bit, HasStdEnc] in {
let Predicates = [NotFP64bit, HasStdEnc, IsNotNaCl] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
}

1
lib/Target/Mips/MipsInstrInfo.td
View File

@ -187,6 +187,7 @@ def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
AssemblerPredicate<"!FeatureMicroMips">;
def IsLE : Predicate<"Subtarget.isLittle()">;
def IsBE : Predicate<"!Subtarget.isLittle()">;
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
let Predicates = [HasStdEnc];

2
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
RM(_RM), OverrideMode(NoOverride), TM(_TM)
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
{
std::string CPUName = CPU;
if (CPUName.empty())

3
lib/Target/Mips/MipsSubtarget.h
View File

@ -125,6 +125,7 @@ protected:
MipsTargetMachine *TM;
Triple TargetTriple;
public:
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
@ -207,6 +208,8 @@ public:
bool os16() const { return Os16;};
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
// for now constant islands are on for the whole compilation unit but we only
// really use them if in addition we are in mips16 mode
//

6
test/CodeGen/Mips/fp-indexed-ls.ll
View File

@ -1,4 +1,6 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-NACL
%struct.S = type <{ [4 x float] }>
%struct.S2 = type <{ [4 x double] }>
@ -13,6 +15,7 @@
define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
entry:
; CHECK: lwxc1
; CHECK-NACL-NOT: lwxc1
%arrayidx = getelementptr inbounds float* %b, i32 %o
%0 = load float* %arrayidx, align 4
ret float %0
@ -21,6 +24,7 @@ entry:
define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
entry:
; CHECK: ldxc1
; CHECK-NACL-NOT: ldxc1
%arrayidx = getelementptr inbounds double* %b, i32 %o
%0 = load double* %arrayidx, align 8
ret double %0
@ -37,6 +41,7 @@ entry:
define void @foo3(float* nocapture %b, i32 %o) nounwind {
entry:
; CHECK: swxc1
; CHECK-NACL-NOT: swxc1
%0 = load float* @gf, align 4
%arrayidx = getelementptr inbounds float* %b, i32 %o
store float %0, float* %arrayidx, align 4
@ -46,6 +51,7 @@ entry:
define void @foo4(double* nocapture %b, i32 %o) nounwind {
entry:
; CHECK: sdxc1
; CHECK-NACL-NOT: sdxc1
%0 = load double* @gd, align 8
%arrayidx = getelementptr inbounds double* %b, i32 %o
store double %0, double* %arrayidx, align 8