From d1f16564477965263b231f953116f223159b8b4e Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 19 Jan 2015 07:20:27 +0000 Subject: [PATCH] [PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2 Our PPC64 ELF V2 call lowering logic added r2 as an operand to all direct call instructions in order to represent the dependency on the TOC base pointer value. Restricting this to ELF V2, however, does not seem to make sense: calls under ELF V1 have the same dependence, and indirect calls have an r2 dependence just as direct ones. Make sure the dependence is noted for all calls under both ELF V1 and ELF V2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCFastISel.cpp | 5 +++-- lib/Target/PowerPC/PPCISelLowering.cpp | 18 +++++++++++++++--- test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll | 4 ++-- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp index 7af601e8f73..791dbbc5c42 100644 --- a/lib/Target/PowerPC/PPCFastISel.cpp +++ b/lib/Target/PowerPC/PPCFastISel.cpp @@ -1524,8 +1524,9 @@ bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) { for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) MIB.addReg(RegArgs[II], RegState::Implicit); - // Direct calls in the ELFv2 ABI need the TOC register live into the call. - if (PPCSubTarget->isELFv2ABI()) + // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live + // into the call. + if (!CLI.IsPatchPoint) MIB.addReg(PPC::X2, RegState::Implicit); // Add a register mask with the call-preserved registers. Proper diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 2001e427705..d1317b7925c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3823,8 +3823,9 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); - // Direct calls in the ELFv2 ABI need the TOC register live into the call. - if (Callee.getNode() && isELFv2ABI && !IsPatchPoint) + // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live + // into the call. + if (isSVR4ABI && isPPC64 && !IsPatchPoint) Ops.push_back(DAG.getRegister(PPC::X2, PtrVT)); return CallOpc; @@ -7368,8 +7369,19 @@ MachineBasicBlock * PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { if (MI->getOpcode() == TargetOpcode::STACKMAP || - MI->getOpcode() == TargetOpcode::PATCHPOINT) + MI->getOpcode() == TargetOpcode::PATCHPOINT) { + if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() && + MI->getOpcode() == TargetOpcode::PATCHPOINT) { + // Call lowering should have added an r2 operand to indicate a dependence + // on the TOC base pointer value. It can't however, because there is no + // way to mark the dependence as implicit there, and so the stackmap code + // will confuse it with a regular operand. Instead, add the dependence + // here. + MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true)); + } + return emitPatchPoint(MI, BB); + } if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 || MI->getOpcode() == PPC::EH_SjLj_SetJmp64) { diff --git a/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll index 687fb9dde29..57577f90109 100644 --- a/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll +++ b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll @@ -15,10 +15,10 @@ entry: ; INVFUNCDESC-DAG: ld [[REG3:[0-9]+]], 0(3) ; INVFUNCDESC: %for.body +; INVFUNCDESC: std 2, 40(1) ; INVFUNCDESC-DAG: mtctr [[REG3]] ; INVFUNCDESC-DAG: mr 11, [[REG2]] -; INVFUNCDESC-DAG: std 2, 40(1) -; INVFUNCDESC: mr 2, [[REG1]] +; INVFUNCDESC-DAG: mr 2, [[REG1]] ; INVFUNCDESC: bctrl ; INVFUNCDESC-NEXT: ld 2, 40(1)