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Added an alternate form of register-register CMP

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to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82081 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan 2009-09-16 21:11:23 +00:00
parent 713f043c16
commit d2125a03af
2 changed files with 8 additions and 0 deletions
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2
lib/Target/X86/X86Instr64bit.td
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@ -1081,6 +1081,8 @@ def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(X86cmp GR64:$src1, GR64:$src2),
(implicit EFLAGS)]>;
def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(X86cmp (loadi64 addr:$src1), GR64:$src2),

6
lib/Target/X86/X86InstrInfo.td
View File

@ -3189,6 +3189,12 @@ def CMP32rm : I<0x3B, MRMSrcMem,
"cmp{l}\t{$src2, $src1|$src1, $src2}",
[(X86cmp GR32:$src1, (loadi32 addr:$src2)),
(implicit EFLAGS)]>;
def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
"cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
"cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
"cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
def CMP8ri : Ii8<0x80, MRM7r,
(outs), (ins GR8:$src1, i8imm:$src2),
"cmp{b}\t{$src2, $src1|$src1, $src2}",