mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
isIntImmediate is a good Idea. Add a flavor that checks bounds while it is at it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22790 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
2d56e72f09
commit
d228427f87
@ -588,6 +588,46 @@ void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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}
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}
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static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
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// test for constant
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// retrieve value
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Imm = CN->getSignExtended();
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// passes muster
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return true;
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}
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// not a constant
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return false;
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}
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// isSIntImmediateBounded - This method tests to see if a constant operand
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// bounded s.t. low <= Imm <= high
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// If so Imm will receive the 64 bit value.
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static bool isSIntImmediateBounded(SDOperand N, int64_t& Imm,
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int64_t low, int64_t high) {
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if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= high)
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return true;
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return false;
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}
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static bool isUIntImmediate(SDOperand N, uint64_t& Imm) {
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// test for constant
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// retrieve value
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Imm = (uint64_t)CN->getValue();
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// passes muster
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return true;
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}
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// not a constant
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return false;
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}
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static bool isUIntImmediateBounded(SDOperand N, uint64_t& Imm,
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uint64_t low, uint64_t high) {
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if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= high)
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return true;
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return false;
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}
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static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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{
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fun = type = offset = 0;
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@ -1072,6 +1112,8 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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unsigned Tmp1, Tmp2 = 0, Tmp3;
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unsigned Opc = 0;
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unsigned opcode = N.getOpcode();
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int64_t SImm;
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uint64_t UImm;
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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@ -1158,18 +1200,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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Select(N.getOperand(0));
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if (ConstantSDNode* CN = dyn_cast<ConstantSDNode>(N.getOperand(1)))
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{
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if (CN->getValue() < 32000)
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{
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BuildMI(BB, Alpha::LDA, 2, Alpha::R30)
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.addImm(-CN->getValue()).addReg(Alpha::R30);
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} else {
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Tmp1 = SelectExpr(N.getOperand(1));
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
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}
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} else {
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if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 32767))
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BuildMI(BB, Alpha::LDA, 2, Alpha::R30).addImm(-SImm).addReg(Alpha::R30);
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else {
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Tmp1 = SelectExpr(N.getOperand(1));
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
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@ -1448,46 +1481,37 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
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bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
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//FIXME: first check for Scaled Adds and Subs!
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ConstantSDNode* CSD = NULL;
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if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(0).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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isSIntImmediateBounded(N.getOperand(0).getOperand(0).getOperand(1), SImm, 2, 3))
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{
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bool use4 = CSD->getValue() == 2;
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bool use4 = SImm == 2;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDL:Alpha::S8ADDL):(use4?Alpha::S4SUBL:Alpha::S8SUBL),
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2,Result).addReg(Tmp1).addReg(Tmp2);
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}
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else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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isSIntImmediateBounded(N.getOperand(0).getOperand(1).getOperand(1), SImm, 2, 3))
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{
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bool use4 = CSD->getValue() == 2;
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bool use4 = SImm == 2;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, use4?Alpha::S4ADDL:Alpha::S8ADDL, 2,Result).addReg(Tmp1).addReg(Tmp2);
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}
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else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() <= 255)
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else if(isSIntImmediateBounded(N.getOperand(0).getOperand(1), SImm, 0, 255))
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
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}
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else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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!isMul &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
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(((int64_t)(CSD->getValue() << 32) >> 32) >= -255) &&
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(((int64_t)(CSD->getValue() << 32) >> 32) <= 0))
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else if(!isMul && isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
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(((SImm << 32) >> 32) >= -255) && (((SImm << 32) >> 32) <= 0))
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{ //handle canonicalization
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Opc = isAdd ? Alpha::SUBLi : Alpha::ADDLi;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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int64_t t = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
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t = 0 - ((t << 32) >> 32);
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assert(t >= 0 && t <= 255);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(t);
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SImm = 0 - ((SImm << 32) >> 32);
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assert(SImm >= 0 && SImm <= 255);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
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}
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else
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{ //Normal add/sub
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@ -1536,8 +1560,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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int dir;
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//Tmp1 = SelectExpr(N.getOperand(0));
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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if(isSIntImmediate(N.getOperand(1), SImm) && SImm <= 255 && SImm >= 0)
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isConst = true;
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switch (CC) {
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@ -1573,8 +1596,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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if (dir == 1) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isConst) {
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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@ -1624,27 +1646,24 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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//constant immediate test
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case ISD::XOR:
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//Match Not
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
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return Result;
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}
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if (isSIntImmediate(N.getOperand(1), SImm) && SImm == -1) {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
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return Result;
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}
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//Fall through
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case ISD::AND:
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//handle zap
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if (opcode == ISD::AND && N.getOperand(1).getOpcode() == ISD::Constant)
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if (opcode == ISD::AND && isUIntImmediate(N.getOperand(1), UImm))
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{
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uint64_t k = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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unsigned int build = 0;
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for(int i = 0; i < 8; ++i)
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{
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if ((k & 0x00FF) == 0x00FF)
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if ((UImm & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((k & 0x00FF) != 0)
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else if ((UImm & 0x00FF) != 0)
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{ build = 0; break; }
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k >>= 8;
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UImm >>= 8;
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}
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if (build)
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{
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@ -1656,9 +1675,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::OR:
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//Check operand(0) == Not
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if (N.getOperand(0).getOpcode() == ISD::XOR &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended()
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== -1) {
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isSIntImmediate(N.getOperand(0).getOperand(1), SImm) && SImm == -1) {
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switch(opcode) {
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case ISD::AND: Opc = Alpha::BIC; break;
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case ISD::OR: Opc = Alpha::ORNOT; break;
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@ -1671,9 +1688,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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//Check operand(1) == Not
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if (N.getOperand(1).getOpcode() == ISD::XOR &&
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended()
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== -1) {
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isSIntImmediate(N.getOperand(1).getOperand(1), SImm) && SImm == -1) {
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switch(opcode) {
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case ISD::AND: Opc = Alpha::BIC; break;
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case ISD::OR: Opc = Alpha::ORNOT; break;
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@ -1689,9 +1704,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::SRL:
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case ISD::SRA:
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case ISD::MUL:
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{
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if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255)) {
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switch(opcode) {
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case ISD::AND: Opc = Alpha::ANDi; break;
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case ISD::OR: Opc = Alpha::BISi; break;
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@ -1702,8 +1715,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::MUL: Opc = Alpha::MULQi; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
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} else {
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switch(opcode) {
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case ISD::AND: Opc = Alpha::AND; break;
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@ -1748,16 +1760,14 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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//first check for Scaled Adds and Subs!
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//Valid for add and sub
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ConstantSDNode* CSD = NULL;
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if(N.getOperand(0).getOpcode() == ISD::SHL &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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if(N.getOperand(0).getOpcode() == ISD::SHL &&
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isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
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(SImm == 2 || SImm == 3)) {
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bool use4 = SImm == 2;
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) && CSD->getValue() <= 255)
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if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
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2, Result).addReg(Tmp2).addImm(CSD->getValue());
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2, Result).addReg(Tmp2).addImm(SImm);
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else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
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@ -1766,45 +1776,37 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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//Position prevents subs
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else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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isSIntImmediate(N.getOperand(1).getOperand(1), SImm) &&
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(SImm == 2 || SImm == 3)) {
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bool use4 = SImm == 2;
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(0))) && CSD->getValue() <= 255)
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BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
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.addImm(CSD->getValue());
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if (isSIntImmediateBounded(N.getOperand(0), SImm, 0, 255))
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BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2).addImm(SImm);
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else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, use4?Alpha::S4ADDQ:Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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}
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//small addi
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else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
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CSD->getValue() <= 255)
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else if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CSD->getValue());
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
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}
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else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
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(int64_t)CSD->getValue() >= 255 &&
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(int64_t)CSD->getValue() <= 0)
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else if(isSIntImmediateBounded(N.getOperand(1), SImm, -255, 0))
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{ //inverted imm add/sub
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Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm((int64_t)CSD->getValue());
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(-SImm);
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}
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//larger addi
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else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
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CSD->getSignExtended() <= 32767 &&
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CSD->getSignExtended() >= -32767)
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else if(isSIntImmediateBounded(N.getOperand(1), SImm, -32767, 32767))
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{ //LDA
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = (long)CSD->getSignExtended();
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if (!isAdd)
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Tmp2 = -Tmp2;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
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SImm = -SImm;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(SImm).addReg(Tmp1);
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}
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//give up and do the operation
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else {
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@ -1825,12 +1827,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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.addReg(Tmp1).addReg(Tmp2);
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return Result;
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} else {
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ConstantSDNode* CSD;
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//check if we can convert into a shift!
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
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(int64_t)CSD->getSignExtended() != 0 &&
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isPowerOf2_64(llabs(CSD->getSignExtended()))) {
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unsigned k = Log2_64(llabs(CSD->getSignExtended()));
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if (isSIntImmediate(N.getOperand(1), SImm) &&
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SImm != 0 && isPowerOf2_64(llabs(SImm))) {
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unsigned k = Log2_64(llabs(SImm));
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Tmp1 = SelectExpr(N.getOperand(0));
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if (k == 1)
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Tmp2 = Tmp1;
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@ -1843,7 +1843,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Alpha::SRLi, 2, Tmp3).addReg(Tmp2).addImm(64-k);
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unsigned Tmp4 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::ADDQ, 2, Tmp4).addReg(Tmp3).addReg(Tmp1);
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if ((int64_t)CSD->getSignExtended() > 0)
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if (SImm > 0)
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BuildMI(BB, Alpha::SRAi, 2, Result).addReg(Tmp4).addImm(k);
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else
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{
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@ -1858,10 +1858,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
|
||||
|
||||
case ISD::UDIV:
|
||||
{
|
||||
ConstantSDNode* CSD;
|
||||
if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
|
||||
((int64_t)CSD->getSignExtended() >= 2 ||
|
||||
(int64_t)CSD->getSignExtended() <= -2))
|
||||
if (isSIntImmediate(N.getOperand(1), SImm) && (SImm >= 2 || SImm <= -2))
|
||||
{
|
||||
// If this is a divide by constant, we can emit code using some magic
|
||||
// constants to implement it as a multiply instead.
|
||||
@ -2007,12 +2004,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
|
||||
if (CC.getOpcode() == ISD::SETCC) {
|
||||
//Int SetCC -> Select
|
||||
//Dropping the CC is only useful if we are comparing to 0
|
||||
if((CC.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0))
|
||||
{
|
||||
if(isSIntImmediateBounded(CC.getOperand(1), SImm, 0, 0)) {
|
||||
//figure out a few things
|
||||
bool useImm = N.getOperand(2).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(2))->getValue() <= 255;
|
||||
bool useImm = isSIntImmediateBounded(N.getOperand(2), SImm, 0, 255);
|
||||
|
||||
//Fix up CC
|
||||
ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
|
||||
@ -2038,9 +2032,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
|
||||
|
||||
if (useImm) {
|
||||
Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
|
||||
.addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
|
||||
.addReg(Tmp1);
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addImm(SImm).addReg(Tmp1);
|
||||
} else {
|
||||
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
||||
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user