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remove broken SRA/rlwimi case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23746 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -145,7 +145,7 @@ static bool isRotateAndMask(unsigned Opcode, unsigned Shift, unsigned Mask,
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if (IsShiftMask) Mask = Mask << Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu << Shift);
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} else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { // shift rights
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} else if (Opcode == ISD::SRL) { // shift rights
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// apply shift to mask if it comes first
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if (IsShiftMask) Mask = Mask >> Shift;
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// determine which bits are made indeterminant by shift
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@ -1125,17 +1125,8 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::SRA:
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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unsigned SH, MB, ME;
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if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
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isRotateAndMask(ISD::SRA, Tmp2, Tmp3, true, SH, MB, ME)) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
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.addImm(MB).addImm(ME);
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 &= 0x1F;
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BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2 & 0x1F);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
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