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ARM assembly parsing for two-operand form of 'mul' instruction.

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Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-11-15 20:02:06 +00:00
parent 908f923cfc
commit d2586daf06
2 changed files with 6 additions and 0 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -5023,3 +5023,7 @@ def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>; cc_out:$s)>;
// 'mul' instruction can be specified with only two operands.
def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
(MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;

2
test/MC/ARM/basic-arm-instructions.s
View File

@@ -1001,11 +1001,13 @@ Lforward:
muls r5, r6, r7 muls r5, r6, r7
mulgt r5, r6, r7 mulgt r5, r6, r7
mulsle r5, r6, r7 mulsle r5, r6, r7
mul r11, r5
@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0] @ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0]
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] @ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0]
@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] @ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0]
@ CHECK: mul r11, r11, r5 @ encoding: [0x9b,0x05,0x0b,0xe0]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------