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Add codegen support for NEON vst2 intrinsics with 128-bit vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-07 18:47:39 +00:00
parent 391e1704c2
commit d285575f87
4 changed files with 84 additions and 7 deletions
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26
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1563,7 +1563,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
VT = N->getOperand(3).getValueType();
if (VT.is64BitVector()) {
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vst2 type");
case MVT::v8i8: Opc = ARM::VST2d8; break;
case MVT::v4i16: Opc = ARM::VST2d16; break;
@ -1575,6 +1577,28 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
N->getOperand(3), N->getOperand(4), Chain };
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
}
// Quad registers are stored as pairs of double registers.
EVT RegVT;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vst2 type");
case MVT::v16i8: Opc = ARM::VST2q8; RegVT = MVT::v8i8; break;
case MVT::v8i16: Opc = ARM::VST2q16; RegVT = MVT::v4i16; break;
case MVT::v4f32: Opc = ARM::VST2q32; RegVT = MVT::v2f32; break;
case MVT::v4i32: Opc = ARM::VST2q32; RegVT = MVT::v2i32; break;
}
SDValue Chain = N->getOperand(0);
SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
N->getOperand(3));
SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
N->getOperand(3));
SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
N->getOperand(4));
SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
N->getOperand(4));
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
D0, D1, D2, D3, Chain };
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
}
case Intrinsic::arm_neon_vst3: {
SDValue MemAddr, MemUpdate, MemOpc;

9
lib/Target/ARM/ARMInstrNEON.td
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@ -316,11 +316,20 @@ let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
class VST2D<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
class VST2Q<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
DPR:$src4), IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
"", []>;
def VST2d8 : VST2D<"vst2.8">;
def VST2d16 : VST2D<"vst2.16">;
def VST2d32 : VST2D<"vst2.32">;
def VST2q8 : VST2Q<"vst2.8">;
def VST2q16 : VST2Q<"vst2.16">;
def VST2q32 : VST2Q<"vst2.32">;
// VST3 : Vector Store (multiple 3-element structures)
class VST3D<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),

7
lib/Target/ARM/NEONPreAllocPass.cpp
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@ -129,6 +129,13 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
NumRegs = 2;
return true;
case ARM::VST2q8:
case ARM::VST2q16:
case ARM::VST2q32:
FirstOpnd = 3;
NumRegs = 4;
return true;
case ARM::VST3d8:
case ARM::VST3d16:
case ARM::VST3d32:

37
test/CodeGen/ARM/vst2.ll
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@ -32,7 +32,44 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind {
ret void
}
define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
;CHECK: vst2Qi8:
;CHECK: vst2.8
%tmp1 = load <16 x i8>* %B
call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1)
ret void
}
define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
;CHECK: vst2Qi16:
;CHECK: vst2.16
%tmp1 = load <8 x i16>* %B
call void @llvm.arm.neon.vst2.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1)
ret void
}
define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
;CHECK: vst2Qi32:
;CHECK: vst2.32
%tmp1 = load <4 x i32>* %B
call void @llvm.arm.neon.vst2.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1)
ret void
}
define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vst2Qf:
;CHECK: vst2.32
%tmp1 = load <4 x float>* %B
call void @llvm.arm.neon.vst2.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1)
ret void
}
declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind
declare void @llvm.arm.neon.vst2.v4i16(i8*, <4 x i16>, <4 x i16>) nounwind
declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>) nounwind
declare void @llvm.arm.neon.vst2.v2f32(i8*, <2 x float>, <2 x float>) nounwind
declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>) nounwind
declare void @llvm.arm.neon.vst2.v8i16(i8*, <8 x i16>, <8 x i16>) nounwind
declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind
declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>) nounwind