From d29bae8bc9b393a24c7f3a1812b88763505eda11 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Wed, 9 Oct 2013 07:53:57 +0000 Subject: [PATCH] AArch64: enable MISched by default. Substantial SelectionDAG scheduling is going away soon, and is interfering with Hao's attempts to implement LDn/STn instructions, so I say we make the leap first. There were a few reorderings (inevitably) which broke some tests. I tried to replace them with CHECK-DAG variants mostly, but some too complex for that to be useful and I just reordered them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64Subtarget.h | 4 +++ test/CodeGen/AArch64/alloca.ll | 22 +++++++-------- test/CodeGen/AArch64/cond-sel.ll | 8 +++--- test/CodeGen/AArch64/fcvt-int.ll | 32 +++++++++++----------- test/CodeGen/AArch64/fp-dp3.ll | 7 ++--- test/CodeGen/AArch64/fp128.ll | 17 ++++++------ test/CodeGen/AArch64/fpimm.ll | 10 ++++--- test/CodeGen/AArch64/func-argpassing.ll | 26 +++++++++--------- test/CodeGen/AArch64/func-calls.ll | 17 ++++++------ test/CodeGen/AArch64/literal_pools.ll | 8 +++--- test/CodeGen/AArch64/tls-dynamics.ll | 36 ++++++++++++------------- test/CodeGen/AArch64/variadic.ll | 9 ++++--- 12 files changed, 102 insertions(+), 94 deletions(-) diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index 4ffb60506cc..f262b946179 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -39,6 +39,10 @@ public: /// AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS); + virtual bool enableMachineScheduler() const { + return true; + } + /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index a84217f86f0..c2f84cdcce6 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -7,13 +7,13 @@ define void @test_simple_alloca(i64 %n) { %buf = alloca i8, i64 %n ; Make sure we align the stack change to 16 bytes: -; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15 -; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0 +; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15 +; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0 ; Make sure we change SP. It would be surprising if anything but x0 were used ; for the final sp, but it could be if it was then moved into x0. -; CHECK: mov [[TMP:x[0-9]+]], sp -; CHECK: sub x0, [[TMP]], [[SPDELTA]] +; CHECK-DAG: mov [[TMP:x[0-9]+]], sp +; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]] ; CHECK: mov sp, x0 call void @use_addr(i8* %buf) @@ -37,13 +37,13 @@ define i64 @test_alloca_with_local(i64 %n) { %loc = alloca i64 %buf = alloca i8, i64 %n ; Make sure we align the stack change to 16 bytes: -; CHECK: add [[SPDELTA:x[0-9]+]], x0, #15 -; CHECK: and x0, [[SPDELTA]], #0xfffffffffffffff0 +; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15 +; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0 ; Make sure we change SP. It would be surprising if anything but x0 were used ; for the final sp, but it could be if it was then moved into x0. -; CHECK: mov [[TMP:x[0-9]+]], sp -; CHECK: sub x0, [[TMP]], [[SPDELTA]] +; CHECK-DAG: mov [[TMP:x[0-9]+]], sp +; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]] ; CHECK: mov sp, x0 ; Obviously suboptimal code here, but it to get &local in x1 @@ -112,16 +112,16 @@ declare i8* @llvm.stacksave() declare void @llvm.stackrestore(i8*) define void @test_scoped_alloca(i64 %n) { -; CHECK: test_scoped_alloca +; CHECK-LABEL: test_scoped_alloca: ; CHECK: sub sp, sp, #32 %sp = call i8* @llvm.stacksave() ; CHECK: mov [[SAVED_SP:x[0-9]+]], sp +; CHECK: mov [[OLDSP:x[0-9]+]], sp %addr = alloca i8, i64 %n ; CHECK: and [[SPDELTA:x[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0 -; CHECK: mov [[OLDSP:x[0-9]+]], sp -; CHECK: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]] +; CHECK-DAG: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]] ; CHECK: mov sp, [[NEWSP]] call void @use_addr(i8* %addr) diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll index 48c50a134bf..3a5b8191a81 100644 --- a/test/CodeGen/AArch64/cond-sel.ll +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -9,16 +9,16 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK: movz [[W52:w[0-9]+]], #52 -; CHECK: movz [[W42:w[0-9]+]], #42 +; CHECK-DAG: movz [[W52:w[0-9]+]], #52 +; CHECK-DAG: movz [[W42:w[0-9]+]], #42 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi %rhs64 = sext i32 %rhs32 to i64 %tst2 = icmp sle i64 %lhs64, %rhs64 %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64 store i64 %val2, i64* @var64 -; CHECK: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw -; CHECK: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]] +; CHECK-DAG: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw +; CHECK-DAG: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]] ; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le ret void diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index 9afcfc4a8b7..b28eb3ea1be 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -5,8 +5,8 @@ define i32 @test_floattoi32(float %in) { %signed = fptosi float %in to i32 %unsigned = fptoui float %in to i32 -; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}} -; CHECK: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}} %res = sub i32 %signed, %unsigned ; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] @@ -20,8 +20,8 @@ define i32 @test_doubletoi32(double %in) { %signed = fptosi double %in to i32 %unsigned = fptoui double %in to i32 -; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}} -; CHECK: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}} %res = sub i32 %signed, %unsigned ; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] @@ -35,8 +35,8 @@ define i64 @test_floattoi64(float %in) { %signed = fptosi float %in to i64 %unsigned = fptoui float %in to i64 -; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}} -; CHECK: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}} %res = sub i64 %signed, %unsigned ; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] @@ -50,8 +50,8 @@ define i64 @test_doubletoi64(double %in) { %signed = fptosi double %in to i64 %unsigned = fptoui double %in to i64 -; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}} -; CHECK: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}} %res = sub i64 %signed, %unsigned ; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] @@ -65,8 +65,8 @@ define float @test_i32tofloat(i32 %in) { %signed = sitofp i32 %in to float %unsigned = uitofp i32 %in to float -; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} -; CHECK: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} %res = fsub float %signed, %unsigned ; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] @@ -79,8 +79,8 @@ define double @test_i32todouble(i32 %in) { %signed = sitofp i32 %in to double %unsigned = uitofp i32 %in to double -; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} -; CHECK: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} %res = fsub double %signed, %unsigned ; CHECK: fsub {{d[0-9]+}}, [[SIG]], [[UNSIG]] @@ -93,8 +93,8 @@ define float @test_i64tofloat(i64 %in) { %signed = sitofp i64 %in to float %unsigned = uitofp i64 %in to float -; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} -; CHECK: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} %res = fsub float %signed, %unsigned ; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] @@ -107,8 +107,8 @@ define double @test_i64todouble(i64 %in) { %signed = sitofp i64 %in to double %unsigned = uitofp i64 %in to double -; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}} -; CHECK: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}} %res = fsub double %signed, %unsigned ; CHECK: sub {{d[0-9]+}}, [[SIG]], [[UNSIG]] diff --git a/test/CodeGen/AArch64/fp-dp3.ll b/test/CodeGen/AArch64/fp-dp3.ll index 3a9a6fc5471..590557f1e8e 100644 --- a/test/CodeGen/AArch64/fp-dp3.ll +++ b/test/CodeGen/AArch64/fp-dp3.ll @@ -129,8 +129,9 @@ define float @test_fnmsub_unfused(float %a, float %b, float %c) { %diff = fsub float %nega, %prod ; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} ; CHECK-NOFAST-NOT: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} -; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} -; CHECK-NOFAST: fneg {{s[0-9]+}}, {{s[0-9]+}} -; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-NOFAST-DAG: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-NOFAST-DAG: fneg {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-NOFAST-DAG: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-NOFAST: ret ret float %diff } diff --git a/test/CodeGen/AArch64/fp128.ll b/test/CodeGen/AArch64/fp128.ll index 853c03d2344..c312bb1917a 100644 --- a/test/CodeGen/AArch64/fp128.ll +++ b/test/CodeGen/AArch64/fp128.ll @@ -150,14 +150,14 @@ define i1 @test_setcc2() { ; Technically, everything after the call to __letf2 is redundant, but we'll let ; LLVM have its fun for now. %val = fcmp ugt fp128 %lhs, %rhs -; CHECK: bl __unordtf2 -; CHECK: mov x[[UNORDERED:[0-9]+]], x0 - ; CHECK: bl __gttf2 ; CHECK: cmp w0, #0 ; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le -; CHECK: cmp w[[UNORDERED]], #0 + +; CHECK: bl __unordtf2 +; CHECK: cmp w0, #0 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq + ; CHECK: orr w0, [[UNORDERED]], [[GT]] ret i1 %val @@ -174,15 +174,14 @@ define i32 @test_br_cc() { ; olt == !uge, which LLVM unfortunately "optimizes" this to. %cond = fcmp olt fp128 %lhs, %rhs -; CHECK: bl __unordtf2 -; CHECK: mov x[[UNORDERED:[0-9]+]], x0 - ; CHECK: bl __getf2 ; CHECK: cmp w0, #0 - ; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt -; CHECK: cmp w[[UNORDERED]], #0 + +; CHECK: bl __unordtf2 +; CHECK: cmp w0, #0 ; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq + ; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]] ; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]] br i1 %cond, label %iftrue, label %iffalse diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll index ccf7c8ae4a3..b8f71695944 100644 --- a/test/CodeGen/AArch64/fpimm.ll +++ b/test/CodeGen/AArch64/fpimm.ll @@ -9,12 +9,13 @@ define void @check_float() { %val = load float* @varf32 %newval1 = fadd float %val, 8.5 store volatile float %newval1, float* @varf32 -; CHECK: fmov {{s[0-9]+}}, #8.5 +; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5 %newval2 = fadd float %val, 128.0 store volatile float %newval2, float* @varf32 -; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI0_0 +; CHECK-DAG: ldr [[HARD:s[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI0_0 +; CHECK: ret ret void } @@ -24,11 +25,12 @@ define void @check_double() { %val = load double* @varf64 %newval1 = fadd double %val, 8.5 store volatile double %newval1, double* @varf64 -; CHECK: fmov {{d[0-9]+}}, #8.5 +; CHECK-DAG: fmov {{d[0-9]+}}, #8.5 %newval2 = fadd double %val, 128.0 store volatile double %newval2, double* @varf64 -; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0 +; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0 +; CHECK: ret ret void } diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index 15f8e768abb..83fc0a0e509 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -35,15 +35,15 @@ define void @take_struct(%myStruct* byval %structval) { %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 - %val0 = load i32* %addr0 + %val0 = load volatile i32* %addr0 ; Some weird move means x0 is used for one access ; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] - store i32 %val0, i32* @var32 + store volatile i32 %val0, i32* @var32 ; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] - %val1 = load i64* %addr1 + %val1 = load volatile i64* %addr1 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] - store i64 %val1, i64* @var64 + store volatile i64 %val1, i64* @var64 ; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] ret void @@ -56,14 +56,14 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 - %val0 = load i32* %addr0 + %val0 = load volatile i32* %addr0 ; Some weird move means x0 is used for one access ; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16 ; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12] store i32 %val0, i32* @var32 ; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] - %val1 = load i64* %addr1 + %val1 = load volatile i64* %addr1 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] store i64 %val1, i64* @var64 ; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] @@ -130,17 +130,17 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var double %notstacked) { ; CHECK-LABEL: struct_on_stack: %addr = getelementptr %myStruct* %struct, i64 0, i32 0 - %val64 = load i64* %addr - store i64 %val64, i64* @var64 + %val64 = load volatile i64* %addr + store volatile i64 %val64, i64* @var64 ; Currently nothing on local stack, so struct should be at sp ; CHECK: ldr [[VAL64:x[0-9]+]], [sp] ; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64] - store double %notstacked, double* @vardouble + store volatile double %notstacked, double* @vardouble ; CHECK-NOT: ldr d0 ; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble - %retval = load i32* %stacked + %retval = load volatile i32* %stacked ret i32 %retval ; CHECK: ldr w0, [sp, #16] } @@ -176,10 +176,10 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, ; CHECK: check_i128_stackalign store i128 %stack2, i128* @var128 ; Nothing local on stack in current codegen, so first stack is 16 away -; CHECK: ldr {{x[0-9]+}}, [sp, #16] +; CHECK: add x[[REG:[0-9]+]], sp, #16 +; CHECK: ldr {{x[0-9]+}}, [x[[REG]], #8] ; Important point is that we address sp+24 for second dword -; CHECK: add [[REG:x[0-9]+]], sp, #16 -; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8] +; CHECK: ldr {{x[0-9]+}}, [sp, #16] ret void } diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index b12130b1470..03cd8070a6f 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -21,15 +21,15 @@ define void @simple_args() { %char1 = load i8* @var8 %char2 = load i8* @var8_2 call void @take_i8s(i8 %char1, i8 %char2) -; CHECK: ldrb w0, [{{x[0-9]+}}, #:lo12:var8] -; CHECK: ldrb w1, [{{x[0-9]+}}, #:lo12:var8_2] +; CHECK-DAG: ldrb w0, [{{x[0-9]+}}, #:lo12:var8] +; CHECK-DAG: ldrb w1, [{{x[0-9]+}}, #:lo12:var8_2] ; CHECK: bl take_i8s %float1 = load float* @varfloat %float2 = load float* @varfloat_2 call void @take_floats(float %float1, float %float2) -; CHECK: ldr s1, [{{x[0-9]+}}, #:lo12:varfloat_2] -; CHECK: ldr s0, [{{x[0-9]+}}, #:lo12:varfloat] +; CHECK-DAG: ldr s1, [{{x[0-9]+}}, #:lo12:varfloat_2] +; CHECK-DAG: ldr s0, [{{x[0-9]+}}, #:lo12:varfloat] ; CHECK: bl take_floats ret void @@ -75,16 +75,17 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, float %var8) define void @check_stack_args() { +; CHECK-LABEL: check_stack_args: call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1, i32* @var32, %myStruct* byval @varstruct, i32 999, double 1.0) ; Want to check that the final double is passed in registers and ; that varstruct is passed on the stack. Rather dependent on how a ; memcpy gets created, but the following works for now. -; CHECK: mov x0, sp -; CHECK: str {{w[0-9]+}}, [x0] -; CHECK: str {{w[0-9]+}}, [x0, #12] -; CHECK: fmov d0, +; CHECK: mov x[[SPREG:[0-9]+]], sp +; CHECK-DAG: str {{w[0-9]+}}, [x[[SPREG]]] +; CHECK-DAG: str {{w[0-9]+}}, [x[[SPREG]], #12] +; CHECK-DAG: fmov d0, ; CHECK: bl struct_on_stack call void @stacked_fpu(float -1.0, double 1.0, float 4.0, float 2.0, diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll index b82f29046d3..fb45416ead8 100644 --- a/test/CodeGen/AArch64/literal_pools.ll +++ b/test/CodeGen/AArch64/literal_pools.ll @@ -65,8 +65,7 @@ define void @floating_lits() { %floatval = load float* @varfloat %newfloat = fadd float %floatval, 128.0 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] -; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] -; CHECK: fadd +; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], #:lo12:[[CURLIT]]] ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] @@ -80,8 +79,9 @@ define void @floating_lits() { %doubleval = load double* @vardouble %newdouble = fadd double %doubleval, 129.0 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] -; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] -; CHECK: fadd +; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, [[LIT128]] +; CHECK: fadd {{d[0-9]+}}, {{d[0-9]+}}, [[LIT129]] ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] diff --git a/test/CodeGen/AArch64/tls-dynamics.ll b/test/CodeGen/AArch64/tls-dynamics.ll index 887d2f8c690..68c481ce98b 100644 --- a/test/CodeGen/AArch64/tls-dynamics.ll +++ b/test/CodeGen/AArch64/tls-dynamics.ll @@ -10,8 +10,8 @@ define i32 @test_generaldynamic() { ret i32 %val ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] ; CHECK: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] @@ -19,8 +19,8 @@ define i32 @test_generaldynamic() { ; CHECK: ldr w0, [x[[TP]], x0] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL } @@ -31,8 +31,8 @@ define i32* @test_generaldynamic_addr() { ret i32* @general_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:general_dynamic_var] ; CHECK: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] @@ -40,8 +40,8 @@ define i32* @test_generaldynamic_addr() { ; CHECK: add x0, [[TP]], x0 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL } @@ -55,8 +55,8 @@ define i32 @test_localdynamic() { ret i32 %val ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] @@ -66,8 +66,8 @@ define i32 @test_localdynamic() { ; CHECK: ldr w0, [x0, [[DTP_OFFSET]]] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL } @@ -78,8 +78,8 @@ define i32* @test_localdynamic_addr() { ret i32* @local_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] @@ -89,8 +89,8 @@ define i32* @test_localdynamic_addr() { ; CHECK: add x0, x0, [[DTP_OFFSET]] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC-DAG: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL } @@ -110,8 +110,8 @@ define i32 @test_localdynamic_deduplicate() { ret i32 %sum ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-DAG: add x0, x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-DAG: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], #:tlsdesc_lo12:_TLS_MODULE_BASE_] ; CHECK: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] diff --git a/test/CodeGen/AArch64/variadic.ll b/test/CodeGen/AArch64/variadic.ll index 1c7e3bf3024..cc2a4c37ae3 100644 --- a/test/CodeGen/AArch64/variadic.ll +++ b/test/CodeGen/AArch64/variadic.ll @@ -9,6 +9,7 @@ declare void @llvm.va_start(i8*) define void @test_simple(i32 %n, ...) { ; CHECK-LABEL: test_simple: ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var ; CHECK: mov x[[FPRBASE:[0-9]+]], sp ; CHECK: str q7, [x[[FPRBASE]], #112] ; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]] @@ -21,7 +22,6 @@ define void @test_simple(i32 %n, ...) { %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) -; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var ; CHECK: movn [[VR_OFFS:w[0-9]+]], #127 ; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] ; CHECK: movn [[GR_OFFS:w[0-9]+]], #55 @@ -131,12 +131,13 @@ define void @test_va_copy() { ; Check beginning and end again: ; CHECK: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var] -; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list] - -; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list ; CHECK: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var +; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list] + ; CHECK: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24] +; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list + ; CHECK: str [[BLOCK]], [x[[DEST_LIST]], #24] ret void