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PPCISelLowering.cpp: Fix r162725.

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[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good!

Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162916 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
NAKAMURA Takumi 2012-08-30 15:52:29 +00:00
parent 25f6b5a554
commit d2a35f2937
1 changed files with 5 additions and 1 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -3164,8 +3164,12 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
// Set CR bit 6 to true if this is a vararg call with floating args passed in
// registers.
if (isVarArg) {
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue Ops[] = { Chain, InFlag };
Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
dl, DAG.getVTList(MVT::Other, MVT::Glue), Chain);
dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
InFlag = Chain.getValue(1);
}