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Move pass configuration out of pass constructors: TailDuplicate::PreRegAlloc

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150091 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-08 21:22:30 +00:00
parent a94e635cec
commit d2a7bedbc9
4 changed files with 12 additions and 11 deletions
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2
include/llvm/CodeGen/Passes.h
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@ -272,7 +272,7 @@ namespace llvm {
/// TailDuplicate Pass - Duplicate blocks with unconditional branches
/// into tails of their predecessors.
FunctionPass *createTailDuplicatePass(bool PreRegAlloc = false);
FunctionPass *createTailDuplicatePass();
/// IfConverter Pass - This pass performs machine code if conversion.
FunctionPass *createIfConverterPass();

4
lib/CodeGen/Passes.cpp
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@ -178,7 +178,7 @@ void TargetPassConfig::addMachinePasses() {
// Pre-ra tail duplication.
if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
PM.add(createTailDuplicatePass(true));
PM.add(createTailDuplicatePass());
printAndVerify("After Pre-RegAlloc TailDuplicate");
}
@ -250,7 +250,7 @@ void TargetPassConfig::addMachinePasses() {
// Tail duplication.
if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false));
PM.add(createTailDuplicatePass());
printNoVerify("After TailDuplicate");
}

13
lib/CodeGen/TailDuplication.cpp
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@ -56,10 +56,10 @@ typedef std::vector<std::pair<MachineBasicBlock*,unsigned> > AvailableValsTy;
namespace {
/// TailDuplicatePass - Perform tail duplication.
class TailDuplicatePass : public MachineFunctionPass {
bool PreRegAlloc;
const TargetInstrInfo *TII;
MachineModuleInfo *MMI;
MachineRegisterInfo *MRI;
bool PreRegAlloc;
// SSAUpdateVRs - A list of virtual registers for which to update SSA form.
SmallVector<unsigned, 16> SSAUpdateVRs;
@ -70,8 +70,8 @@ namespace {
public:
static char ID;
explicit TailDuplicatePass(bool PreRA) :
MachineFunctionPass(ID), PreRegAlloc(PreRA) {}
explicit TailDuplicatePass() :
MachineFunctionPass(ID), PreRegAlloc(false) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "Tail Duplication"; }
@ -118,14 +118,15 @@ namespace {
char TailDuplicatePass::ID = 0;
}
FunctionPass *llvm::createTailDuplicatePass(bool PreRegAlloc) {
return new TailDuplicatePass(PreRegAlloc);
FunctionPass *llvm::createTailDuplicatePass() {
return new TailDuplicatePass();
}
bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo();
MRI = &MF.getRegInfo();
MMI = getAnalysisIfAvailable<MachineModuleInfo>();
PreRegAlloc = MRI->isSSA();
bool MadeChange = false;
while (TailDuplicateBlocks(MF))
@ -823,7 +824,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
SmallVector<MachineOperand, 4> PriorCond;
// This has to check PrevBB->succ_size() because EH edges are ignored by
// AnalyzeBranch.
if (PrevBB->succ_size() == 1 &&
if (PrevBB->succ_size() == 1 &&
!TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) &&
PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 &&
!TailBB->hasAddressTaken()) {

4
lib/Target/PTX/PTXTargetMachine.cpp
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@ -284,7 +284,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// Pre-ra tail duplication.
if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(true));
PM.add(createTailDuplicatePass());
printAndVerify("After Pre-RegAlloc TailDuplicate");
}
@ -365,7 +365,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
// Tail duplication.
if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(false));
PM.add(createTailDuplicatePass());
printNoVerify("After TailDuplicate");
}