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https://github.com/c64scene-ar/llvm-6502.git
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int to float conversion and another setcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19855 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -46,7 +46,7 @@ namespace {
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addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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@ -62,10 +62,7 @@ namespace {
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computeRegisterProperties();
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// addLegalFPImmediate(+0.0); // FLD0
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// addLegalFPImmediate(+1.0); // FLD1
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// addLegalFPImmediate(-0.0); // FLD0/FCHS
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// addLegalFPImmediate(-1.0); // FLD1/FCHS
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addLegalFPImmediate(+0.0); //F31
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}
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/// LowerArguments - This hook must be implemented to indicate how we should
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@ -209,13 +206,13 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
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break;
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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break;
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case MVT::f64:
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@ -332,6 +329,17 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0) ||
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CN->isExactlyValue(-0.0)) {
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(R31).addReg(R31);
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} else {
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abort();
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}
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}
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return Result;
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case ISD::FrameIndex:
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
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@ -363,6 +371,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i1: //Treat i1 as i8 since there are problems otherwise
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case MVT::i8:
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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@ -589,10 +598,18 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::SETUGT: Opc = isConst1 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 2; break;
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case ISD::SETULE: Opc = isConst2 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
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case ISD::SETUGE: Opc = isConst1 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 2; break;
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case ISD::SETNE:
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std::cerr << "Alpha does not have a setne.\n";
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abort();
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}
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case ISD::SETNE: {//Handle this one special
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//std::cerr << "Alpha does not have a setne.\n";
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//abort();
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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//and invert
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BuildMI(BB,Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
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return Result;
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}
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}
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if (dir == 1) {
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isConst2) {
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@ -796,14 +813,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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// case ISD::SINT_TO_FP:
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// MVT::ValueType DestTy = N.getValueType();
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// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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// Tmp2 = MakeReg(DestTy);
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// Opc = DestTy == MVT::f64 ? ITOFT : ITOFS;
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// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
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// Opc = DestTy == MVT::f64 ? CVTQT : CVTQS;
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// BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
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case ISD::SINT_TO_FP:
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{
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MVT::ValueType DestTy = N.getValueType();
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assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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Tmp2 = MakeReg(DestTy);
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Opc = DestTy == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
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BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
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Opc = DestTy == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
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return Result;
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}
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// // case ISD::UINT_TO_FP:
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// case ISD::FP_TO_SINT:
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@ -322,6 +322,14 @@ def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Fl
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def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating
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def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //Integer to floating move, T_floating
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//CVTLQ F-P 17.010 Convert longword to quadword
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//CVTQL F-P 17.030 Convert quadword to longword
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def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
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//CVTST F-P 16.2AC Convert S_floating to T_floating
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//CVTTQ F-P 16.0AF Convert T_floating to quadword
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//CVTTS F-P 16.0AC Convert T_floating to S_floating
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//S_floating : IEEE Single
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//T_floating : IEEE Double
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@ -354,14 +362,6 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
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//CMPTLT F-P 16.0A6 Compare T_floating less than
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//CMPTUN F-P 16.0A4 Compare T_floating unordered
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//CVTLQ F-P 17.010 Convert longword to quadword
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//CVTQL F-P 17.030 Convert quadword to longword
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//CVTQS F-P 16.0BC Convert quadword to S_floating
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//CVTQT F-P 16.0BE Convert quadword to T_floating
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//CVTST F-P 16.2AC Convert S_floating to T_floating
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//CVTTQ F-P 16.0AF Convert T_floating to quadword
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//CVTTS F-P 16.0AC Convert T_floating to S_floating
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//FCMOVEQ F-P 17.02A FCMOVE if = zero
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//FCMOVGE F-P 17.02D FCMOVE if >= zero
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//FCMOVGT F-P 17.02F FCMOVE if > zero
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