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int to float conversion and another setcc

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19855 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-01-27 07:50:35 +00:00
parent 1bae291cb9
commit d2bb960d8c
2 changed files with 54 additions and 32 deletions
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70
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -46,7 +46,7 @@ namespace {
addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); //Should this be Promote? Chris?
setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
@ -62,10 +62,7 @@ namespace {
computeRegisterProperties();
// addLegalFPImmediate(+0.0); // FLD0
// addLegalFPImmediate(+1.0); // FLD1
// addLegalFPImmediate(-0.0); // FLD0/FCHS
// addLegalFPImmediate(-1.0); // FLD1/FCHS
addLegalFPImmediate(+0.0); //F31
}
/// LowerArguments - This hook must be implemented to indicate how we should
@ -209,13 +206,13 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
case MVT::i8:
case MVT::i16:
case MVT::i32:
// Promote the integer to 64 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (Args[i].second->isSigned())
Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
else
Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
break;
// Promote the integer to 64 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (Args[i].second->isSigned())
Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
else
Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
break;
case MVT::i64:
break;
case MVT::f64:
@ -332,6 +329,17 @@ unsigned ISel::SelectExpr(SDOperand N) {
Node->dump();
assert(0 && "Node not handled!\n");
case ISD::ConstantFP:
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
if (CN->isExactlyValue(+0.0) ||
CN->isExactlyValue(-0.0)) {
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(R31).addReg(R31);
} else {
abort();
}
}
return Result;
case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
@ -363,6 +371,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i16:
BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
break;
case MVT::i1: //Treat i1 as i8 since there are problems otherwise
case MVT::i8:
BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
break;
@ -589,10 +598,18 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::SETUGT: Opc = isConst1 ? Alpha::CMPULTi : Alpha::CMPULT; dir = 2; break;
case ISD::SETULE: Opc = isConst2 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
case ISD::SETUGE: Opc = isConst1 ? Alpha::CMPULEi : Alpha::CMPULE; dir = 2; break;
case ISD::SETNE:
std::cerr << "Alpha does not have a setne.\n";
abort();
}
case ISD::SETNE: {//Handle this one special
//std::cerr << "Alpha does not have a setne.\n";
//abort();
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
//and invert
BuildMI(BB,Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
return Result;
}
}
if (dir == 1) {
Tmp1 = SelectExpr(N.getOperand(0));
if (isConst2) {
@ -796,14 +813,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
// case ISD::SINT_TO_FP:
// MVT::ValueType DestTy = N.getValueType();
// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
// Tmp2 = MakeReg(DestTy);
// Opc = DestTy == MVT::f64 ? ITOFT : ITOFS;
// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
// Opc = DestTy == MVT::f64 ? CVTQT : CVTQS;
// BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
case ISD::SINT_TO_FP:
{
MVT::ValueType DestTy = N.getValueType();
assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
Tmp2 = MakeReg(DestTy);
Opc = DestTy == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
Opc = DestTy == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
}
// // case ISD::UINT_TO_FP:
// case ISD::FP_TO_SINT:

16
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -322,6 +322,14 @@ def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Fl
def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating
def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //Integer to floating move, T_floating
//CVTLQ F-P 17.010 Convert longword to quadword
//CVTQL F-P 17.030 Convert quadword to longword
def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
//CVTST F-P 16.2AC Convert S_floating to T_floating
//CVTTQ F-P 16.0AF Convert T_floating to quadword
//CVTTS F-P 16.0AC Convert T_floating to S_floating
//S_floating : IEEE Single
//T_floating : IEEE Double
@ -354,14 +362,6 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
//CMPTLT F-P 16.0A6 Compare T_floating less than
//CMPTUN F-P 16.0A4 Compare T_floating unordered
//CVTLQ F-P 17.010 Convert longword to quadword
//CVTQL F-P 17.030 Convert quadword to longword
//CVTQS F-P 16.0BC Convert quadword to S_floating
//CVTQT F-P 16.0BE Convert quadword to T_floating
//CVTST F-P 16.2AC Convert S_floating to T_floating
//CVTTQ F-P 16.0AF Convert T_floating to quadword
//CVTTS F-P 16.0AC Convert T_floating to S_floating
//FCMOVEQ F-P 17.02A FCMOVE if = zero
//FCMOVGE F-P 17.02D FCMOVE if >= zero
//FCMOVGT F-P 17.02F FCMOVE if > zero