6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-22 13:29:44 +00:00
Code Issues Projects Releases Wiki Activity

Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2012-09-11 23:32:17 +00:00
parent 2a3fcb382e
commit d2c699706c
3 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
utils/TableGen/CodeGenRegisters.cpp
View File

@ -993,6 +993,12 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
for (unsigned i = 0, e = Registers.size(); i != e; ++i) for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i]->buildObjectGraph(*this); Registers[i]->buildObjectGraph(*this);
// Compute register name map.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
RegistersByName.GetOrCreateValue(
Registers[i]->TheDef->getValueAsString("AsmName"),
Registers[i]);
// Precompute all sub-register maps. // Precompute all sub-register maps.
// This will create Composite entries for all inferred sub-register indices. // This will create Composite entries for all inferred sub-register indices.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) for (unsigned i = 0, e = Registers.size(); i != e; ++i)

4
utils/TableGen/CodeGenRegisters.h
View File

@ -440,6 +440,7 @@ namespace llvm {
// Registers. // Registers.
std::vector<CodeGenRegister*> Registers; std::vector<CodeGenRegister*> Registers;
StringMap<CodeGenRegister*> RegistersByName;
DenseMap<Record*, CodeGenRegister*> Def2Reg; DenseMap<Record*, CodeGenRegister*> Def2Reg;
unsigned NumNativeRegUnits; unsigned NumNativeRegUnits;
@ -522,6 +523,9 @@ namespace llvm {
} }
const std::vector<CodeGenRegister*> &getRegisters() { return Registers; } const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}
// Find a register from its Record def. // Find a register from its Record def.
CodeGenRegister *getReg(Record*); CodeGenRegister *getReg(Record*);

11
utils/TableGen/CodeGenTarget.cpp
View File

@ -199,12 +199,11 @@ void CodeGenTarget::ReadRegAltNameIndices() const {
/// getRegisterByName - If there is a register with the specific AsmName, /// getRegisterByName - If there is a register with the specific AsmName,
/// return it. /// return it.
const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
if (Regs[i]->TheDef->getValueAsString("AsmName") == Name) if (I == Regs.end())
return Regs[i]; return 0;
return I->second;
return 0;
} }
std::vector<MVT::SimpleValueType> CodeGenTarget:: std::vector<MVT::SimpleValueType> CodeGenTarget::