6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-20 16:17:38 +00:00
Code Issues Projects Releases Wiki Activity

Remove the IA-64 backend.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-07-24 00:30:09 +00:00
parent 5ff58b5c3a
commit d2cb3d2c32
53 changed files with 13 additions and 4544 deletions
Download Patch File Download Diff File Expand all files Collapse all files
docs/CodeGenerator.html
+3 -3
View File
@@ -1380,9 +1380,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
for <tt>RegisterClass</tt>, the last parameter of which is a list of
registers. Just commenting some out is one simple way to avoid them being
used. A more polite way is to explicitly exclude some registers from
the <i>allocation order</i>. See the definition of the <tt>GR</tt> register
class in <tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
</p>
<p>Virtual registers are also denoted by integer numbers. Contrary to physical
registers, different virtual registers never share the same number. The