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Add shift and small immediate support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24778 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -250,22 +250,28 @@ def XNORCCri: F3_2<2, 0b010111,
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sll $b, $c, $dst", []>;
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sll $b, $c, $dst", []>;
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"srl $b, $c, $dst", []>;
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"srl $b, $c, $dst", []>;
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sra $b, $c, $dst", []>;
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sla $b, $c, $dst", []>;
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000,
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@ -556,3 +562,11 @@ def FCMPES : F3_3<2, 0b110101, 0b001010101,
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def FCMPED : F3_3<2, 0b110101, 0b001010110,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmped $src1, $src2\n\tnop">;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// Small immediates.
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def : Pat<(i32 simm13:$val),
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(ORri G0, imm:$val)>;
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@ -250,22 +250,28 @@ def XNORCCri: F3_2<2, 0b010111,
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sll $b, $c, $dst", []>;
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sll $b, $c, $dst", []>;
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"srl $b, $c, $dst", []>;
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"srl $b, $c, $dst", []>;
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sra $b, $c, $dst", []>;
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sla $b, $c, $dst", []>;
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000,
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@ -556,3 +562,11 @@ def FCMPES : F3_3<2, 0b110101, 0b001010101,
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def FCMPED : F3_3<2, 0b110101, 0b001010110,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmped $src1, $src2\n\tnop">;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// Small immediates.
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def : Pat<(i32 simm13:$val),
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(ORri G0, imm:$val)>;
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