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https://github.com/c64scene-ar/llvm-6502.git
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Implement computeKnownBits for min/max nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239378 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
0f59d850fa
commit
d2f17c4e2b
@ -2432,6 +2432,19 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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KnownOne = KnownOne.trunc(BitWidth);
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break;
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}
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case ISD::SMIN:
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case ISD::SMAX:
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case ISD::UMIN:
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case ISD::UMAX: {
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APInt Op0Zero, Op0One;
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APInt Op1Zero, Op1One;
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computeKnownBits(Op.getOperand(0), Op0Zero, Op0One, Depth);
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computeKnownBits(Op.getOperand(1), Op1Zero, Op1One, Depth);
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KnownZero = Op0Zero & Op1Zero;
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KnownOne = Op0One & Op1One;
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break;
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}
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case ISD::FrameIndex:
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case ISD::TargetFrameIndex:
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if (unsigned Align = InferPtrAlignment(Op)) {
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@ -2535,7 +2548,15 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
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if (Tmp == 1) return 1; // Early out.
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Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1);
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return std::min(Tmp, Tmp2);
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case ISD::SMIN:
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case ISD::SMAX:
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case ISD::UMIN:
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case ISD::UMAX:
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
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if (Tmp == 1)
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return 1; // Early out.
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Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth + 1);
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return std::min(Tmp, Tmp2);
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case ISD::SADDO:
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case ISD::UADDO:
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case ISD::SSUBO:
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@ -115,3 +115,54 @@ define void @s_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Make sure redundant and removed
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; FUNC-LABEL: {{^}}simplify_demanded_bits_test_umax_ugt_i16:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: s_max_u32 [[MIN:s[0-9]+]], [[A]], [[B]]
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; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]]
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; SI-NEXT: buffer_store_dword [[VMIN]]
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define void @simplify_demanded_bits_test_umax_ugt_i16(i32 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) nounwind {
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%a.ext = zext i16 %a to i32
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%b.ext = zext i16 %b to i32
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%cmp = icmp ugt i32 %a.ext, %b.ext
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%val = select i1 %cmp, i32 %a.ext, i32 %b.ext
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%mask = and i32 %val, 65535
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store i32 %mask, i32 addrspace(1)* %out
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ret void
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}
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; Make sure redundant sign_extend_inreg removed.
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; FUNC-LABEL: {{^}}simplify_demanded_bits_test_min_slt_i16:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: s_max_i32 [[MIN:s[0-9]+]], [[A]], [[B]]
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; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]]
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; SI-NEXT: buffer_store_dword [[VMIN]]
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define void @simplify_demanded_bits_test_min_slt_i16(i32 addrspace(1)* %out, i16 signext %a, i16 signext %b) nounwind {
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%a.ext = sext i16 %a to i32
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%b.ext = sext i16 %b to i32
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%cmp = icmp sgt i32 %a.ext, %b.ext
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%val = select i1 %cmp, i32 %a.ext, i32 %b.ext
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%shl = shl i32 %val, 16
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%sextinreg = ashr i32 %shl, 16
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store i32 %sextinreg, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Should get match min/max through extends inserted by
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; legalization.
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; FUNC-LABEL: {{^}}s_test_imin_sge_i16:
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; SI: s_sext_i32_i16
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; SI: s_sext_i32_i16
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; SI: v_cmp_ge_i32_e32
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; SI: v_cndmask_b32
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define void @s_test_imin_sge_i16(i16 addrspace(1)* %out, i16 %a, i16 %b) nounwind {
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%cmp = icmp sge i16 %a, %b
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%val = select i1 %cmp, i16 %a, i16 %b
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store i16 %val, i16 addrspace(1)* %out
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ret void
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}
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@ -136,3 +136,54 @@ define void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0, i1 addrspace
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store i1 %cmp, i1 addrspace(1)* %outgep1
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ret void
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}
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; Make sure redundant and removed
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; FUNC-LABEL: {{^}}simplify_demanded_bits_test_umin_ult_i16:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: s_min_u32 [[MIN:s[0-9]+]], [[A]], [[B]]
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; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]]
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; SI-NEXT: buffer_store_dword [[VMIN]]
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define void @simplify_demanded_bits_test_umin_ult_i16(i32 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) nounwind {
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%a.ext = zext i16 %a to i32
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%b.ext = zext i16 %b to i32
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%cmp = icmp ult i32 %a.ext, %b.ext
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%val = select i1 %cmp, i32 %a.ext, i32 %b.ext
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%mask = and i32 %val, 65535
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store i32 %mask, i32 addrspace(1)* %out
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ret void
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}
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; Make sure redundant sign_extend_inreg removed.
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; FUNC-LABEL: {{^}}simplify_demanded_bits_test_min_slt_i16:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: s_min_i32 [[MIN:s[0-9]+]], [[A]], [[B]]
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; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]]
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; SI-NEXT: buffer_store_dword [[VMIN]]
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define void @simplify_demanded_bits_test_min_slt_i16(i32 addrspace(1)* %out, i16 signext %a, i16 signext %b) nounwind {
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%a.ext = sext i16 %a to i32
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%b.ext = sext i16 %b to i32
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%cmp = icmp slt i32 %a.ext, %b.ext
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%val = select i1 %cmp, i32 %a.ext, i32 %b.ext
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%shl = shl i32 %val, 16
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%sextinreg = ashr i32 %shl, 16
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store i32 %sextinreg, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Should get match min/max through extends inserted by
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; legalization.
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; FUNC-LABEL: {{^}}s_test_imin_sle_i16:
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; SI: s_sext_i32_i16
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; SI: s_sext_i32_i16
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; SI: v_cmp_le_i32_e32
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; SI: v_cndmask_b32
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define void @s_test_imin_sle_i16(i16 addrspace(1)* %out, i16 %a, i16 %b) nounwind {
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%cmp = icmp sle i16 %a, %b
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%val = select i1 %cmp, i16 %a, i16 %b
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store i16 %val, i16 addrspace(1)* %out
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ret void
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}
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@ -450,13 +450,10 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x
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ret void
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}
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; FIXME: The BFE should really be eliminated. I think it should happen
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; when computeKnownBitsForTargetNode is implemented for imax.
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; FUNC-LABEL: {{^}}sext_in_reg_to_illegal_type:
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; SI: buffer_load_sbyte
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; SI: v_max_i32
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; SI: v_bfe_i32
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; SI-NOT: bfe
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; SI: buffer_store_short
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define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
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%tmp5 = load i8, i8 addrspace(1)* %src, align 1
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