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Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
3cede2d0b2
commit
d2fbdb7f5c
@ -1868,14 +1868,15 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
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let Pattern = pattern;
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list<Predicate> Predicates = [HasNEON];
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bits<5> Vd;
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bits<4> Rt;
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bits<5> V;
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bits<4> R;
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bits<4> p;
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bits<4> lane;
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let Inst{31-28} = p{3-0};
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let Inst{7} = Vd{4};
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let Inst{19-16} = Vd{3-0};
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let Inst{15-12} = Rt{3-0};
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let Inst{7} = V{4};
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let Inst{19-16} = V{3-0};
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let Inst{15-12} = R{3-0};
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}
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class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
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dag oops, dag iops, InstrItinClass itin,
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@ -3501,30 +3501,44 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
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// VMOV : Vector Get Lane (move scalar to ARM core register)
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def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
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imm:$lane))]>;
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(outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
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[(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
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imm:$lane))]> {
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let Inst{21} = lane{2};
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let Inst{6-5} = lane{1-0};
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}
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def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
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imm:$lane))]>;
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(outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
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[(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
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imm:$lane))]> {
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let Inst{21} = lane{1};
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let Inst{6} = lane{0};
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}
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def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
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imm:$lane))]>;
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(outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
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[(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
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imm:$lane))]> {
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let Inst{21} = lane{2};
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let Inst{6-5} = lane{1-0};
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}
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def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
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[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
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imm:$lane))]>;
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(outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
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[(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
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imm:$lane))]> {
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let Inst{21} = lane{1};
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let Inst{6} = lane{0};
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}
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def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
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(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
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[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
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imm:$lane))]>;
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(outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
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IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
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[(set GPR:$R, (extractelt (v2i32 DPR:$V),
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imm:$lane))]> {
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let Inst{21} = lane{0};
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}
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// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
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def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
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(VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
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@ -3560,22 +3574,30 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
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// VMOV : Vector Set Lane (move ARM core register to scalar)
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let Constraints = "$src1 = $dst" in {
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def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
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[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
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[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
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(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
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[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
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GPR:$src2, imm:$lane))]>;
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let Constraints = "$src1 = $V" in {
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def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
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(ins DPR:$src1, GPR:$R, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
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[(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
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GPR:$R, imm:$lane))]> {
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let Inst{21} = lane{2};
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let Inst{6-5} = lane{1-0};
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}
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def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
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(ins DPR:$src1, GPR:$R, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
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[(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
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GPR:$R, imm:$lane))]> {
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let Inst{21} = lane{1};
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let Inst{6} = lane{0};
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}
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def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
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(ins DPR:$src1, GPR:$R, nohash_imm:$lane),
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IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
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[(set DPR:$V, (insertelt (v2i32 DPR:$src1),
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GPR:$R, imm:$lane))]> {
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let Inst{21} = lane{0};
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}
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}
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def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
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(v16i8 (INSERT_SUBREG QPR:$src1,
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@ -304,4 +304,128 @@ declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
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define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
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%tmp2 = extractelement <8 x i8> %tmp1, i32 1
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%tmp3 = sext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
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%tmp2 = extractelement <4 x i16> %tmp1, i32 1
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%tmp3 = sext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
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%tmp2 = extractelement <8 x i8> %tmp1, i32 1
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%tmp3 = zext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
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%tmp2 = extractelement <4 x i16> %tmp1, i32 1
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%tmp3 = zext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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; Do a vector add to keep the extraction from being done directly from memory.
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define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = add <2 x i32> %tmp1, %tmp1
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; CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
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%tmp3 = extractelement <2 x i32> %tmp2, i32 1
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ret i32 %tmp3
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}
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define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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; CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
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%tmp2 = extractelement <16 x i8> %tmp1, i32 1
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%tmp3 = sext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
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%tmp2 = extractelement <8 x i16> %tmp1, i32 1
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%tmp3 = sext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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; CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
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%tmp2 = extractelement <16 x i8> %tmp1, i32 1
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%tmp3 = zext i8 %tmp2 to i32
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ret i32 %tmp3
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}
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define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
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%tmp2 = extractelement <8 x i16> %tmp1, i32 1
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%tmp3 = zext i16 %tmp2 to i32
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ret i32 %tmp3
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}
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; Do a vector add to keep the extraction from being done directly from memory.
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define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = add <4 x i32> %tmp1, %tmp1
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; CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
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%tmp3 = extractelement <4 x i32> %tmp2, i32 1
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ret i32 %tmp3
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}
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define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee]
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%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee
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%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee]
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%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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; CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee]
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%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee]
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%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee]
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
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ret <4 x i32> %tmp2
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}
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