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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
250305156a
commit
d344c6bcf9
@ -126,8 +126,10 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FROUND, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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// The hardware supports ROTR, but not ROTL
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// The hardware supports 32-bit ROTR, but not ROTL.
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i64, Expand);
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setOperationAction(ISD::ROTR, MVT::i64, Expand);
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// Lower floating point store/load to integer store/load to reduce the number
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// of patterns in tablegen.
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@ -264,11 +266,13 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::MUL, VT, Expand);
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setOperationAction(ISD::OR, VT, Expand);
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setOperationAction(ISD::SHL, VT, Expand);
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::SRL, VT, Expand);
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setOperationAction(ISD::SRA, VT, Expand);
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setOperationAction(ISD::SRL, VT, Expand);
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setOperationAction(ISD::ROTL, VT, Expand);
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setOperationAction(ISD::ROTR, VT, Expand);
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setOperationAction(ISD::SUB, VT, Expand);
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::SELECT, VT, Expand);
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@ -52,9 +52,6 @@ private:
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MachineRegisterInfo & MRI, unsigned dword_offset) const;
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SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
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/// \brief Lower ROTL opcode to BITALIGN
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SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
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34
test/CodeGen/R600/rotl.i64.ll
Normal file
34
test/CodeGen/R600/rotl.i64.ll
Normal file
@ -0,0 +1,34 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: @s_rotl_i64:
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; SI: S_LSHL_B64
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; SI: S_SUB_I32
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; SI: S_LSHR_B64
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; SI: S_OR_B64
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define void @s_rotl_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
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entry:
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%0 = shl i64 %x, %y
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%1 = sub i64 64, %y
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%2 = lshr i64 %x, %1
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%3 = or i64 %0, %2
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store i64 %3, i64 addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: @v_rotl_i64:
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; SI: V_LSHL_B64
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; SI: V_SUB_I32
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; SI: V_LSHR_B64
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; SI: V_OR_B32
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; SI: V_OR_B32
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define void @v_rotl_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
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entry:
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%x = load i64 addrspace(1)* %xptr, align 8
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%y = load i64 addrspace(1)* %yptr, align 8
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%tmp0 = shl i64 %x, %y
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%tmp1 = sub i64 64, %y
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%tmp2 = lshr i64 %x, %tmp1
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%tmp3 = or i64 %tmp0, %tmp2
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store i64 %tmp3, i64 addrspace(1)* %in, align 8
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ret void
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}
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54
test/CodeGen/R600/rotl.ll
Normal file
54
test/CodeGen/R600/rotl.ll
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@ -0,0 +1,54 @@
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: @rotl_i32:
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; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
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; R600-NEXT: 32
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; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
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; SI: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}}
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; SI: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]]
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; SI: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]]
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define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = shl i32 %x, %y
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%1 = sub i32 32, %y
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%2 = lshr i32 %x, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: @rotl_v2i32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
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entry:
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%0 = shl <2 x i32> %x, %y
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%1 = sub <2 x i32> <i32 32, i32 32>, %y
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%2 = lshr <2 x i32> %x, %1
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%3 = or <2 x i32> %0, %2
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store <2 x i32> %3, <2 x i32> addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: @rotl_v4i32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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; SI: S_SUB_I32
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; SI: V_ALIGNBIT_B32
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define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
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entry:
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%0 = shl <4 x i32> %x, %y
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%1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
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%2 = lshr <4 x i32> %x, %1
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%3 = or <4 x i32> %0, %2
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store <4 x i32> %3, <4 x i32> addrspace(1)* %in
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ret void
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}
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@ -1,37 +1,52 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; R600-CHECK-LABEL: @rotr:
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; R600-CHECK: BIT_ALIGN_INT
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; FUNC-LABEL: @rotr_i32:
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; R600: BIT_ALIGN_INT
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; SI-CHECK-LABEL: @rotr:
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; SI-CHECK: V_ALIGNBIT_B32
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define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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; SI: V_ALIGNBIT_B32
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define void @rotr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = sub i32 32, %y
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%1 = shl i32 %x, %0
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%2 = lshr i32 %x, %y
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%3 = or i32 %1, %2
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store i32 %3, i32 addrspace(1)* %in
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%tmp0 = sub i32 32, %y
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%tmp1 = shl i32 %x, %tmp0
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%tmp2 = lshr i32 %x, %y
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%tmp3 = or i32 %tmp1, %tmp2
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store i32 %tmp3, i32 addrspace(1)* %in
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ret void
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}
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; R600-CHECK-LABEL: @rotl:
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; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
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; R600-CHECK-NEXT: 32
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; R600-CHECK: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
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; FUNC-LABEL: @rotr_v2i32:
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; SI-CHECK-LABEL: @rotl:
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; SI-CHECK: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}}
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; SI-CHECK: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]]
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; SI-CHECK: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]]
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define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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; SI: V_ALIGNBIT_B32
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; SI: V_ALIGNBIT_B32
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define void @rotr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
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entry:
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%0 = shl i32 %x, %y
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%1 = sub i32 32, %y
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%2 = lshr i32 %x, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %in
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%tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
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%tmp1 = shl <2 x i32> %x, %tmp0
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%tmp2 = lshr <2 x i32> %x, %y
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%tmp3 = or <2 x i32> %tmp1, %tmp2
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store <2 x i32> %tmp3, <2 x i32> addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: @rotr_v4i32:
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; SI: V_ALIGNBIT_B32
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; SI: V_ALIGNBIT_B32
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; SI: V_ALIGNBIT_B32
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; SI: V_ALIGNBIT_B32
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define void @rotr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
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entry:
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%tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
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%tmp1 = shl <4 x i32> %x, %tmp0
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%tmp2 = lshr <4 x i32> %x, %y
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%tmp3 = or <4 x i32> %tmp1, %tmp2
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store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %in
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ret void
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}
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