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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Added isel patterns for RET, JMP, and WRITEPORT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24588 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -43,6 +43,9 @@ def i32i8imm : Operand<i32>;
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let PrintMethod = "printCallOperand" in
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def calltarget : Operand<i32>;
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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@ -183,33 +186,33 @@ let isTerminator = 1 in
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//
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// Return instructions.
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<0xC3, RawFrm, (ops), "ret", []>;
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
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def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
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def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1 in
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class IBr<bits<8> opcode, dag ops, string asm> :
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I<opcode, RawFrm, ops, asm, []>;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in
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class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
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I<opcode, RawFrm, ops, asm, pattern>;
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let isBarrier = 1 in
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def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
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def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
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def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
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def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
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def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
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def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
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def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
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def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
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def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
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def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB;
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def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB;
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def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
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def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
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def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
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def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
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def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
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def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
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[]>, TB;
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def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", []>, TB;
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def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", []>, TB;
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def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", []>, TB;
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def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", []>, TB;
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def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", []>, TB;
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def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB;
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def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB;
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def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB;
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def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
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def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", []>, TB;
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def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", []>, TB;
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def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", []>, TB;
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def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", []>, TB;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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@ -225,7 +228,7 @@ let isCall = 1 in
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">;
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def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>;
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>;
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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@ -315,26 +318,37 @@ def IN16rr : I<0xED, RawFrm, (ops),
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def IN32rr : I<0xED, RawFrm, (ops),
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"in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
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def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
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def IN8ri : Ii8<0xE4, RawFrm, (ops i8imm:$port),
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"in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>;
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def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
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def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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"in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize;
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def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
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def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}", []>, Imp<[DX, AL], []>;
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def OUT16rr : I<0xEF, RawFrm, (ops),
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"out{w} {%ax, %dx|%DX, %AX}", []>, Imp<[DX, AX], []>, OpSize;
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def OUT32rr : I<0xEF, RawFrm, (ops),
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"out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>;
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let hasCtrlDep=1 in {
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}",
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[(writeport (i8 AL), (i16 DX))]>, Imp<[DX, AL], []>;
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def OUT16rr : I<0xEF, RawFrm, (ops),
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"out{w} {%ax, %dx|%DX, %AX}",
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[(writeport (i16 AX), (i16 DX))]>, Imp<[DX, AX], []>, OpSize;
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def OUT32rr : I<0xEF, RawFrm, (ops),
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"out{l} {%eax, %dx|%DX, %EAX}",
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[(writeport (i32 EAX), (i16 DX))]>, Imp<[DX, EAX], []>;
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def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
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"out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>;
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def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
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"out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize;
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def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
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"out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>;
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def OUT8ir : Ii8<0xE6, RawFrm, (ops i8imm:$port),
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"out{b} {%al, $port|$port, %AL}",
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[(writeport (i8 AL), (i8 imm:$port))]>,
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Imp<[AL], []>;
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def OUT16ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
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"out{w} {%ax, $port|$port, %AX}",
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[(writeport (i16 AX), (i8 imm:$port))]>,
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Imp<[AX], []>, OpSize;
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def OUT32ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
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"out{l} {%eax, $port|$port, %EAX}",
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[(writeport (i32 EAX), (i8 imm:$port))]>,
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Imp<[EAX], []>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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