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Replace V_SET0 with variants for each SSE execution domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99975 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -287,7 +287,9 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
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case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SET0: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
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case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
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case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
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case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
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case X86::MOV16r0:
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@ -2514,7 +2514,9 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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Alignment = (*LoadMI->memoperands_begin())->getAlignment();
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else
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switch (LoadMI->getOpcode()) {
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case X86::V_SET0:
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case X86::V_SET0PS:
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case X86::V_SET0PD:
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case X86::V_SET0PI:
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case X86::V_SETALLONES:
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Alignment = 16;
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break;
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@ -2544,11 +2546,13 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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SmallVector<MachineOperand,X86AddrNumOperands> MOs;
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switch (LoadMI->getOpcode()) {
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case X86::V_SET0:
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case X86::V_SET0PS:
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case X86::V_SET0PD:
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case X86::V_SET0PI:
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case X86::V_SETALLONES:
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case X86::FsFLD0SD:
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case X86::FsFLD0SS: {
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// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
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// Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
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// Create a constant-pool entry and operands to load from it.
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// Medium and large mode can't fold loads this way.
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@ -3675,6 +3679,7 @@ static const unsigned ReplaceableInstrs[][3] = {
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{ X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
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{ X86::ORPSrm, X86::ORPDrm, X86::PORrm },
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{ X86::ORPSrr, X86::ORPDrr, X86::PORrr },
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{ X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
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{ X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
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{ X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
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};
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@ -1115,15 +1115,19 @@ def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
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// load of an all-zeros value if folding it would be beneficial.
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// FIXME: Change encoding to pseudo!
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1 in
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def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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isCodeGenOnly = 1 in {
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def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4f32 immAllZerosV))]>;
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def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v2f64 immAllZerosV))]>;
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let ExeDomain = SSEPackedInt in
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def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllZerosV))]>;
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}
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def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
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def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
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def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
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def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
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def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
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def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
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def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
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def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
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def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
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@ -3026,14 +3030,14 @@ let Predicates = [HasSSE2] in {
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let AddedComplexity = 15 in {
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// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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(MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
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(MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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(MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
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(MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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(MOVSSrr (v4f32 (V_SET0)),
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(MOVSSrr (v4f32 (V_SET0PS)),
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(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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(MOVSSrr (v4i32 (V_SET0)),
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(MOVSSrr (v4i32 (V_SET0PI)),
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(EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
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}
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
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; RUN: grep xorps %t | count 1
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; RUN: grep pxor %t | count 1
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; RUN: grep movaps %t | count 1
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; RUN: not grep shuf %t
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
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; RUN: grep xorps %t | count 1
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; RUN: grep pxor %t | count 1
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; RUN: not grep shufps %t
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define void @test() {
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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define <4 x i32> @test(i8** %ptr) {
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; CHECK: xorps
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; CHECK: pxor
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; CHECK: punpcklbw
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; CHECK: punpcklwd
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@ -1,5 +1,6 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xorps | count 2
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; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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; CHECK: xorps
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define void @foo(<4 x float>* %P) {
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%T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
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%S = fadd <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1]
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@ -7,6 +8,7 @@ define void @foo(<4 x float>* %P) {
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ret void
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}
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; CHECK: pxor
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define void @bar(<4 x i32>* %P) {
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%T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1]
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%S = add <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1]
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@ -1,5 +1,4 @@
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; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
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; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
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; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 2
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; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2
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@M1 = external global <1 x i64>
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@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind {
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ret <4 x i32> %tmp
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; X32: test1:
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; X32: xorps %xmm0, %xmm0
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; X32: pxor %xmm0, %xmm0
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; X32: ret
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}
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