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Added a check so that if we have two machine instructions in this form

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MOV R0, R1
    MOV R1, R0

the second machine instruction is removed. Added a regression test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2006-08-21 07:33:33 +00:00
parent 8ea5ecb056
commit d36d03bf2d
2 changed files with 45 additions and 10 deletions
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lib/CodeGen/VirtRegMap.cpp
+30 -10
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@@ -521,6 +521,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// Process all of the spilled uses and all non spilled reg references.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || MO.getReg() == 0)
continue; // Ignore non-register operands.
@@ -790,16 +791,37 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
}
if (!OpTakenCareOf) {
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.
unsigned Src, Dst;
if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
++NumDCE;
DEBUG(std::cerr << "Removing now-noop copy: " << MI);
MBB.erase(&MI);
VRM.RemoveFromFoldedVirtMap(&MI);
goto ProcessNextInst;
if (TII->isMoveInstr(MI, Src, Dst)) {
if (Src == Dst) {
// Check to see if this is a noop copy. If so, eliminate
// the instruction before considering the dest reg to be
// changed.
++NumDCE;
DEBUG(std::cerr << "Removing now-noop copy: " << MI);
MBB.erase(&MI);
VRM.RemoveFromFoldedVirtMap(&MI);
goto ProcessNextInst;
} else if (MII != MBB.begin()) {
// Check to see if this is a sequence of the form:
// mov R0, R1
// mov R1, R0
// Eliminate the second move if so.
MachineBasicBlock::iterator PrevMII = MII; --PrevMII;
MachineInstr& PrevMI = *PrevMII;
unsigned PrevSrc, PrevDst;
if (TII->isMoveInstr(PrevMI, PrevSrc, PrevDst))
if (PrevSrc == Dst && PrevDst == Src) {
++NumDCE;
DEBUG(std::cerr << "Removing now-noop copy: " << MI);
MBB.erase(&MI);
VRM.RemoveFromFoldedVirtMap(&MI);
goto ProcessNextInst;
}
}
}
Spills.ClobberPhysReg(VirtReg);
continue;
}
@@ -861,8 +883,6 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
}
}
llvm::Spiller* llvm::createSpiller() {
switch (SpillerOpt) {
default: assert(0 && "Unreachable!");