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Set correct <def,undef> flags when lowering REG_SEQUENCE.

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A REG_SEQUENCE instruction is lowered into a sequence of partial defs:

  %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
  %vreg7:ssub_1<def> = COPY %vreg2
  %vreg7:ssub_2<def> = COPY %vreg2
  %vreg7:ssub_3<def> = COPY %vreg2

The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write.  Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.

This fixes PR11841.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-01-24 23:28:42 +00:00
parent 1ce6a36610
commit d36f5af224
3 changed files with 90 additions and 1 deletions
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46
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1646,6 +1646,36 @@ static void UpdateRegSequenceSrcs(unsigned SrcReg,
}
}
// Find the first def of Reg, assuming they are all in the same basic block.
static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
SmallPtrSet<MachineInstr*, 8> Defs;
MachineInstr *First = 0;
for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg);
MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI))
First = MI;
if (!First)
return 0;
MachineBasicBlock *MBB = First->getParent();
MachineBasicBlock::iterator A = First, B = First;
bool Moving;
do {
Moving = false;
if (A != MBB->begin()) {
Moving = true;
--A;
if (Defs.erase(A)) First = A;
}
if (B != MBB->end()) {
Defs.erase(B);
++B;
Moving = true;
}
} while (Moving && !Defs.empty());
assert(Defs.empty() && "Instructions outside basic block!");
return First;
}
/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
/// EXTRACT_SUBREG from the same register and to the same virtual register
/// with different sub-register indices, attempt to combine the
@ -1874,6 +1904,22 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
}
// Set <def,undef> flags on the first DstReg def in the basic block.
// It marks the beginning of the live range. All the other defs are
// read-modify-write.
if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
MachineOperand &MO = Def->getOperand(i);
if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
MO.setIsUndef();
}
// Make sure there is a full non-subreg imp-def operand on the
// instruction. This shouldn't be necessary, but it seems that at least
// RAFast requires it.
Def->addRegisterDefined(DstReg, TRI);
DEBUG(dbgs() << "First def: " << *Def);
}
if (IsImpDef) {
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));

2
test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
View File

@ -12,7 +12,7 @@ target triple = "thumbv7-apple-darwin10"
; CHECK: vld1.64 {d16, d17}, [r{{.}}]
; CHECK-NOT: vld1.64 {d16, d17}
; CHECK: vmov.f64 d19, d16
; CHECK: vmov.f64
define i32 @test(i8* %arg) nounwind {
entry:

43
test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
; PR11841
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-eabi"
; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
bb:
%tmp = load <2 x float>* undef, align 8, !tbaa !0
%tmp2 = extractelement <2 x float> %tmp, i32 0
%tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
%tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
%tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2
%tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
%tmp7 = extractelement <2 x float> %tmp, i32 1
%tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1
%tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2
%tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3
%tmp11 = bitcast <4 x float> %tmp6 to <2 x i64>
%tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp13 = bitcast <1 x i64> %tmp12 to <2 x float>
%tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer
%tmp15 = bitcast <4 x float> %tmp14 to <2 x i64>
%tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
%tmp18 = extractelement <2 x float> %tmp17, i32 0
tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
%tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
%tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
%tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
%tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
%tmp26 = extractelement <2 x float> %tmp25, i32 0
tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
ret void
}
declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}